drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/athub/athub_3_0_0_sh_mask.h- Extension
.h- Size
- 133669 bytes
- Lines
- 1247
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _athub_3_0_0_SH_MASK_HEADER
#define _athub_3_0_0_SH_MASK_HEADER
// addressBlock: athub_xpbdec
//XPB_RTR_SRC_APRTR0
#define XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR1
#define XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR2
#define XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR3
#define XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR4
#define XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR5
#define XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR6
#define XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR7
#define XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR8
#define XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR9
#define XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR10
#define XPB_RTR_SRC_APRTR10__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR10__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR11
#define XPB_RTR_SRC_APRTR11__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR11__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR12
#define XPB_RTR_SRC_APRTR12__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR12__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_SRC_APRTR13
#define XPB_RTR_SRC_APRTR13__BASE_ADDR__SHIFT 0x0
#define XPB_RTR_SRC_APRTR13__BASE_ADDR_MASK 0x7FFFFFFFL
//XPB_RTR_DEST_MAP0
#define XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
#define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
#define XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
#define XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
#define XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
#define XPB_RTR_DEST_MAP0__NMR_MASK 0x00000001L
#define XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0x000FFFFEL
#define XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0x00F00000L
#define XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x01000000L
#define XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x02000000L
#define XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7C000000L
//XPB_RTR_DEST_MAP1
#define XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
#define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
#define XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
#define XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
#define XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
#define XPB_RTR_DEST_MAP1__NMR_MASK 0x00000001L
#define XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0x000FFFFEL
#define XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0x00F00000L
#define XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x01000000L
#define XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x02000000L
#define XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7C000000L
//XPB_RTR_DEST_MAP2
#define XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
#define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
#define XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
#define XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
#define XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
#define XPB_RTR_DEST_MAP2__NMR_MASK 0x00000001L
#define XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0x000FFFFEL
#define XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0x00F00000L
#define XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x01000000L
#define XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x02000000L
#define XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7C000000L
//XPB_RTR_DEST_MAP3
#define XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
#define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
#define XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.