drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_d.h
Extension: .h
Size: 26278 bytes
Lines: 662
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef BIF_3_0_D_H
#define BIF_3_0_D_H

#define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C
#define ixPB0_DFT_JIT_INJ_REG0 0x13000
#define ixPB0_DFT_JIT_INJ_REG1 0x13004
#define ixPB0_DFT_JIT_INJ_REG2 0x13008
#define ixPB0_GLB_CTRL_REG0 0x10004
#define ixPB0_GLB_CTRL_REG1 0x10008
#define ixPB0_GLB_CTRL_REG2 0x1000C
#define ixPB0_GLB_CTRL_REG3 0x10010
#define ixPB0_GLB_CTRL_REG4 0x10014
#define ixPB0_GLB_CTRL_REG5 0x10018
#define ixPB0_GLB_OVRD_REG0 0x10030
#define ixPB0_GLB_OVRD_REG1 0x10034
#define ixPB0_GLB_OVRD_REG2 0x10038
#define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x1001C
#define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x10020
#define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x10024
#define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x10028
#define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x1002C
#define ixPB0_HW_DEBUG 0x12004
#define ixPB0_PIF_CNTL 0x0010
#define ixPB0_PIF_CNTL2 0x0014
#define ixPB0_PIF_HW_DEBUG 0x0002
#define ixPB0_PIF_PAIRING 0x0011
#define ixPB0_PIF_PDNB_OVERRIDE_0 0x0020
#define ixPB0_PIF_PDNB_OVERRIDE_10 0x0032
#define ixPB0_PIF_PDNB_OVERRIDE_1 0x0021
#define ixPB0_PIF_PDNB_OVERRIDE_11 0x0033
#define ixPB0_PIF_PDNB_OVERRIDE_12 0x0034
#define ixPB0_PIF_PDNB_OVERRIDE_13 0x0035
#define ixPB0_PIF_PDNB_OVERRIDE_14 0x0036
#define ixPB0_PIF_PDNB_OVERRIDE_15 0x0037
#define ixPB0_PIF_PDNB_OVERRIDE_2 0x0022
#define ixPB0_PIF_PDNB_OVERRIDE_3 0x0023
#define ixPB0_PIF_PDNB_OVERRIDE_4 0x0024
#define ixPB0_PIF_PDNB_OVERRIDE_5 0x0025
#define ixPB0_PIF_PDNB_OVERRIDE_6 0x0026
#define ixPB0_PIF_PDNB_OVERRIDE_7 0x0027
#define ixPB0_PIF_PDNB_OVERRIDE_8 0x0030
#define ixPB0_PIF_PDNB_OVERRIDE_9 0x0031
#define ixPB0_PIF_PWRDOWN_0 0x0012
#define ixPB0_PIF_PWRDOWN_1 0x0013
#define ixPB0_PIF_PWRDOWN_2 0x0017
#define ixPB0_PIF_PWRDOWN_3 0x0018
#define ixPB0_PIF_SC_CTL 0x0016
#define ixPB0_PIF_SCRATCH 0x0001
#define ixPB0_PIF_SEQ_STATUS_0 0x0028
#define ixPB0_PIF_SEQ_STATUS_10 0x003A
#define ixPB0_PIF_SEQ_STATUS_1 0x0029
#define ixPB0_PIF_SEQ_STATUS_11 0x003B
#define ixPB0_PIF_SEQ_STATUS_12 0x003C
#define ixPB0_PIF_SEQ_STATUS_13 0x003D
#define ixPB0_PIF_SEQ_STATUS_14 0x003E
#define ixPB0_PIF_SEQ_STATUS_15 0x003F
#define ixPB0_PIF_SEQ_STATUS_2 0x002A
#define ixPB0_PIF_SEQ_STATUS_3 0x002B
#define ixPB0_PIF_SEQ_STATUS_4 0x002C
#define ixPB0_PIF_SEQ_STATUS_5 0x002D
#define ixPB0_PIF_SEQ_STATUS_6 0x002E
#define ixPB0_PIF_SEQ_STATUS_7 0x002F
#define ixPB0_PIF_SEQ_STATUS_8 0x0038
#define ixPB0_PIF_SEQ_STATUS_9 0x0039
#define ixPB0_PIF_TXPHYSTATUS 0x0015
#define ixPB0_PLL_LC0_CTRL_REG0 0x14480
#define ixPB0_PLL_LC0_OVRD_REG0 0x14490
#define ixPB0_PLL_LC0_OVRD_REG1 0x14494
#define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500
#define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504
#define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508
#define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C
#define ixPB0_PLL_RO0_CTRL_REG0 0x14440
#define ixPB0_PLL_RO0_OVRD_REG0 0x14450
#define ixPB0_PLL_RO0_OVRD_REG1 0x14454
#define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460
#define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464
#define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468
#define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C
#define ixPB0_PLL_RO_GLB_CTRL_REG0 0x14000
#define ixPB0_PLL_RO_GLB_OVRD_REG0 0x14010
#define ixPB0_RX_GLB_CTRL_REG0 0x16000
#define ixPB0_RX_GLB_CTRL_REG1 0x16004
#define ixPB0_RX_GLB_CTRL_REG2 0x16008
#define ixPB0_RX_GLB_CTRL_REG3 0x1600C
#define ixPB0_RX_GLB_CTRL_REG4 0x16010
#define ixPB0_RX_GLB_CTRL_REG5 0x16014
#define ixPB0_RX_GLB_CTRL_REG6 0x16018
#define ixPB0_RX_GLB_CTRL_REG7 0x1601C
#define ixPB0_RX_GLB_CTRL_REG8 0x16020

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.