drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h

Extension

.h

Size

558393 bytes

Lines

8128

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef BIF_3_0_SH_MASK_H
#define BIF_3_0_SH_MASK_H

#define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
#define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
#define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
#define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
#define BACO_CNTL__BACO_EN_MASK 0x00000001L
#define BACO_CNTL__BACO_EN__SHIFT 0x00000000
#define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
#define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
#define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
#define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
#define BACO_CNTL__BACO_MODE_MASK 0x00000040L
#define BACO_CNTL__BACO_MODE__SHIFT 0x00000006
#define BACO_CNTL__BACO_POWER_OFF_MASK 0x00000008L
#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x00000003
#define BACO_CNTL__BACO_RESET_EN_MASK 0x00000010L
#define BACO_CNTL__BACO_RESET_EN__SHIFT 0x00000004
#define BACO_CNTL__PWRGOOD_BF_MASK 0x00000200L
#define BACO_CNTL__PWRGOOD_BF__SHIFT 0x00000009
#define BACO_CNTL__PWRGOOD_DVO_MASK 0x00001000L
#define BACO_CNTL__PWRGOOD_DVO__SHIFT 0x0000000c
#define BACO_CNTL__PWRGOOD_GPIO_MASK 0x00000400L
#define BACO_CNTL__PWRGOOD_GPIO__SHIFT 0x0000000a
#define BACO_CNTL__PWRGOOD_MEM_MASK 0x00000800L
#define BACO_CNTL__PWRGOOD_MEM__SHIFT 0x0000000b
#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK 0x00000100L
#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x00000008
#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK_MASK 0x00000001L
#define BF_ANA_ISO_CNTL__BF_ANA_ISO_DIS_MASK__SHIFT 0x00000000
#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK_MASK 0x00000002L
#define BF_ANA_ISO_CNTL__BF_VDDC_ISO_DIS_MASK__SHIFT 0x00000001
#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG_MASK 0x00000001L
#define BIF_BACO_DEBUG__BIF_BACO_SCANDUMP_FLG__SHIFT 0x00000000
#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG_MASK 0x00000001L
#define BIF_BACO_DEBUG_LATCH__BIF_BACO_LATCH_FLG__SHIFT 0x00000000
#define BIF_BACO_MSIC__BIF_XTALIN_SEL_MASK 0x00000001L
#define BIF_BACO_MSIC__BIF_XTALIN_SEL__SHIFT 0x00000000
#define BIF_BUSNUM_CNTL1__ID_MASK_MASK 0x000000ffL
#define BIF_BUSNUM_CNTL1__ID_MASK__SHIFT 0x00000000
#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK 0x00000100L
#define BIF_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x00000008
#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK 0x000000ffL
#define BIF_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x00000000
#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK 0x00020000L
#define BIF_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x00000011
#define BIF_BUSNUM_CNTL2__HDPREG_CNTL_MASK 0x00010000L
#define BIF_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x00000010
#define BIF_BUSNUM_LIST0__ID0_MASK 0x000000ffL
#define BIF_BUSNUM_LIST0__ID0__SHIFT 0x00000000
#define BIF_BUSNUM_LIST0__ID1_MASK 0x0000ff00L
#define BIF_BUSNUM_LIST0__ID1__SHIFT 0x00000008
#define BIF_BUSNUM_LIST0__ID2_MASK 0x00ff0000L
#define BIF_BUSNUM_LIST0__ID2__SHIFT 0x00000010
#define BIF_BUSNUM_LIST0__ID3_MASK 0xff000000L
#define BIF_BUSNUM_LIST0__ID3__SHIFT 0x00000018
#define BIF_BUSNUM_LIST1__ID4_MASK 0x000000ffL
#define BIF_BUSNUM_LIST1__ID4__SHIFT 0x00000000
#define BIF_BUSNUM_LIST1__ID5_MASK 0x0000ff00L
#define BIF_BUSNUM_LIST1__ID5__SHIFT 0x00000008
#define BIF_BUSNUM_LIST1__ID6_MASK 0x00ff0000L
#define BIF_BUSNUM_LIST1__ID6__SHIFT 0x00000010
#define BIF_BUSNUM_LIST1__ID7_MASK 0xff000000L
#define BIF_BUSNUM_LIST1__ID7__SHIFT 0x00000018
#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK 0x0000003fL
#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x00000000
#define BIF_CLK_PDWN_DELAY_TIMER__TIMER_MASK 0x000003ffL
#define BIF_CLK_PDWN_DELAY_TIMER__TIMER__SHIFT 0x00000000
#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1_MASK 0x00000010L
#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK1__SHIFT 0x00000004
#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2_MASK 0x00000020L
#define BIF_DEBUG_CNTL__DEBUG_BYTESEL_BLK2__SHIFT 0x00000005
#define BIF_DEBUG_CNTL__DEBUG_EN_MASK 0x00000001L
#define BIF_DEBUG_CNTL__DEBUG_EN__SHIFT 0x00000000
#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1_MASK 0x00001f00L
#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x00000008
#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2_MASK 0x001f0000L
#define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK2__SHIFT 0x00000010
#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP_MASK 0x01000000L
#define BIF_DEBUG_CNTL__DEBUG_IDSEL_XSP__SHIFT 0x00000018
#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN_MASK 0x00000002L
#define BIF_DEBUG_CNTL__DEBUG_MULTIBLOCKEN__SHIFT 0x00000001
#define BIF_DEBUG_CNTL__DEBUG_OUT_EN_MASK 0x00000004L
#define BIF_DEBUG_CNTL__DEBUG_OUT_EN__SHIFT 0x00000002
#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x00000008L
#define BIF_DEBUG_CNTL__DEBUG_PAD_SEL__SHIFT 0x00000003
#define BIF_DEBUG_CNTL__DEBUG_SWAP_MASK 0x00000080L
#define BIF_DEBUG_CNTL__DEBUG_SWAP__SHIFT 0x00000007
#define BIF_DEBUG_CNTL__DEBUG_SYNC_CLKSEL_MASK 0xc0000000L

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.