drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_d.h- Extension
.h- Size
- 80325 bytes
- Lines
- 923
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef BIF_4_1_D_H
#define BIF_4_1_D_H
#define mmMM_INDEX 0x0
#define mmMM_INDEX_HI 0x6
#define mmMM_DATA 0x1
#define mmCC_BIF_BX_FUSESTRAP0 0x14D7
#define mmBUS_CNTL 0x1508
#define mmCONFIG_CNTL 0x1509
#define mmCONFIG_MEMSIZE 0x150a
#define mmCONFIG_F0_BASE 0x150b
#define mmCONFIG_APER_SIZE 0x150c
#define mmCONFIG_REG_APER_SIZE 0x150d
#define mmBIF_SCRATCH0 0x150e
#define mmBIF_SCRATCH1 0x150f
#define mmBX_RESET_EN 0x1514
#define mmMM_CFGREGS_CNTL 0x1513
#define mmHW_DEBUG 0x1515
#define mmMASTER_CREDIT_CNTL 0x1516
#define mmSLAVE_REQ_CREDIT_CNTL 0x1517
#define mmBX_RESET_CNTL 0x1518
#define mmINTERRUPT_CNTL 0x151a
#define mmINTERRUPT_CNTL2 0x151b
#define mmBIF_DEBUG_CNTL 0x151c
#define mmBIF_DEBUG_MUX 0x151d
#define mmBIF_DEBUG_OUT 0x151e
#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528
#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520
#define mmCLKREQB_PAD_CNTL 0x1521
#define mmSMBUS_SLV_CNTL 0x14fd
#define mmSMBUS_SLV_CNTL1 0x14fe
#define mmSMBDAT_PAD_CNTL 0x1522
#define mmSMBCLK_PAD_CNTL 0x1523
#define mmBIF_XDMA_LO 0x14c0
#define mmBIF_XDMA_HI 0x14c1
#define mmBIF_FEATURES_CONTROL_MISC 0x14c2
#define mmBIF_DOORBELL_CNTL 0x14c3
#define mmBIF_SLVARB_MODE 0x14c4
#define mmBIF_FB_EN 0x1524
#define mmBIF_BUSNUM_CNTL1 0x1525
#define mmBIF_BUSNUM_LIST0 0x1526
#define mmBIF_BUSNUM_LIST1 0x1527
#define mmBIF_BUSNUM_CNTL2 0x152b
#define mmBIF_BUSY_DELAY_CNTR 0x1529
#define mmBIF_PERFMON_CNTL 0x152c
#define mmBIF_PERFCOUNTER0_RESULT 0x152d
#define mmBIF_PERFCOUNTER1_RESULT 0x152e
#define mmSLAVE_HANG_PROTECTION_CNTL 0x1536
#define mmGPU_HDP_FLUSH_REQ 0x1537
#define mmGPU_HDP_FLUSH_DONE 0x1538
#define mmSLAVE_HANG_ERROR 0x153b
#define mmCAPTURE_HOST_BUSNUM 0x153c
#define mmHOST_BUSNUM 0x153d
#define mmPEER_REG_RANGE0 0x153e
#define mmPEER_REG_RANGE1 0x153f
#define mmPEER0_FB_OFFSET_HI 0x14f3
#define mmPEER0_FB_OFFSET_LO 0x14f2
#define mmPEER1_FB_OFFSET_HI 0x14f1
#define mmPEER1_FB_OFFSET_LO 0x14f0
#define mmPEER2_FB_OFFSET_HI 0x14ef
#define mmPEER2_FB_OFFSET_LO 0x14ee
#define mmPEER3_FB_OFFSET_HI 0x14ed
#define mmPEER3_FB_OFFSET_LO 0x14ec
#define mmDBG_BYPASS_SRBM_ACCESS 0x14eb
#define mmSMBUS_BACO_DUMMY 0x14c6
#define mmBIF_DEVFUNCNUM_LIST0 0x14e8
#define mmBIF_DEVFUNCNUM_LIST1 0x14e7
#define mmBACO_CNTL 0x14e5
#define mmBF_ANA_ISO_CNTL 0x14c7
#define mmMEM_TYPE_CNTL 0x14e4
#define mmBIF_BACO_DEBUG 0x14df
#define mmBIF_BACO_DEBUG_LATCH 0x14dc
#define mmBACO_CNTL_MISC 0x14db
#define mmBIF_SSA_PWR_STATUS 0x14c8
#define mmBIF_SSA_GFX0_LOWER 0x14ca
#define mmBIF_SSA_GFX0_UPPER 0x14cb
#define mmBIF_SSA_GFX1_LOWER 0x14cc
#define mmBIF_SSA_GFX1_UPPER 0x14cd
#define mmBIF_SSA_GFX2_LOWER 0x14ce
#define mmBIF_SSA_GFX2_UPPER 0x14cf
#define mmBIF_SSA_GFX3_LOWER 0x14d0
#define mmBIF_SSA_GFX3_UPPER 0x14d1
#define mmBIF_SSA_DISP_LOWER 0x14d2
#define mmBIF_SSA_DISP_UPPER 0x14d3
#define mmBIF_SSA_MC_LOWER 0x14d4
#define mmBIF_SSA_MC_UPPER 0x14d5
#define mmIMPCTL_RESET 0x14f5
#define mmGARLIC_FLUSH_CNTL 0x1401
#define mmGARLIC_FLUSH_ADDR_START_0 0x1402
#define mmGARLIC_FLUSH_ADDR_START_1 0x1404Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.