drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

Extension

.h

Size

696066 bytes

Lines

11497

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef BIF_5_0_SH_MASK_H
#define BIF_5_0_SH_MASK_H

#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
#define MM_INDEX__MM_OFFSET__SHIFT 0x0
#define MM_INDEX__MM_APER_MASK 0x80000000
#define MM_INDEX__MM_APER__SHIFT 0x1f
#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
#define MM_DATA__MM_DATA_MASK 0xffffffff
#define MM_DATA__MM_DATA__SHIFT 0x0
#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK    0x2
#define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT  0x1
#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK 0x1
#define BIF_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0
#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1
#define BUS_CNTL__PMI_IO_DIS_MASK 0x4
#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
#define BUS_CNTL__PMI_BM_DIS_MASK 0x10
#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
#define BUS_CNTL__PMI_INT_DIS_MASK 0x20
#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5
#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40
#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80
#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00
#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
#define BUS_CNTL__SET_MC_TC_MASK 0xe000
#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000
#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000
#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000
#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1
#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
#define CONFIG_CNTL__VGA_DIS_MASK 0x2
#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1
#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18
#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff
#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
#define CONFIG_RESERVED__CONFIG_RESERVED_MASK 0xffffffff
#define CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0
#define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK 0x1
#define BIF_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0
#define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK 0x80000000
#define BIF_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f
#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff
#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff
#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff
#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff
#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff
#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT_MASK 0x1
#define BIF_RLC_INTR_CNTL__RLC_HVCMD_INTERRUPT__SHIFT 0x0
#define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT_MASK 0x100
#define BIF_RLC_INTR_CNTL__RLC_VM_IDLE_INTERRUPT__SHIFT 0x8
#define BIF_BME_STATUS__DMA_ON_BME_LOW_MASK 0x1
#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0
#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK 0x10000
#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10
#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK 0x1
#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0
#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK 0x2
#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1
#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK 0x10000
#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10
#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK 0x20000
#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11
#define BX_RESET_EN__COR_RESET_EN_MASK 0x1
#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
#define BX_RESET_EN__REG_RESET_EN_MASK 0x2

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.