drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h- Extension
.h- Size
- 2103101 bytes
- Lines
- 33081
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef BIF_5_1_SH_MASK_H
#define BIF_5_1_SH_MASK_H
#define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
#define MM_INDEX__MM_OFFSET__SHIFT 0x0
#define MM_INDEX__MM_APER_MASK 0x80000000
#define MM_INDEX__MM_APER__SHIFT 0x1f
#define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
#define MM_DATA__MM_DATA_MASK 0xffffffff
#define MM_DATA__MM_DATA__SHIFT 0x0
#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
#define BUS_CNTL__BIOS_ROM_WRT_EN_MASK 0x1
#define BUS_CNTL__BIOS_ROM_WRT_EN__SHIFT 0x0
#define BUS_CNTL__BIOS_ROM_DIS_MASK 0x2
#define BUS_CNTL__BIOS_ROM_DIS__SHIFT 0x1
#define BUS_CNTL__PMI_IO_DIS_MASK 0x4
#define BUS_CNTL__PMI_IO_DIS__SHIFT 0x2
#define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
#define BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3
#define BUS_CNTL__PMI_BM_DIS_MASK 0x10
#define BUS_CNTL__PMI_BM_DIS__SHIFT 0x4
#define BUS_CNTL__PMI_INT_DIS_MASK 0x20
#define BUS_CNTL__PMI_INT_DIS__SHIFT 0x5
#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK 0x40
#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6
#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK 0x80
#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7
#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN_MASK 0x100
#define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
#define BUS_CNTL__SET_AZ_TC_MASK 0x1c00
#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa
#define BUS_CNTL__SET_MC_TC_MASK 0xe000
#define BUS_CNTL__SET_MC_TC__SHIFT 0xd
#define BUS_CNTL__ZERO_BE_WR_EN_MASK 0x10000
#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10
#define BUS_CNTL__ZERO_BE_RD_EN_MASK 0x20000
#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11
#define BUS_CNTL__RD_STALL_IO_WR_MASK 0x40000
#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12
#define CONFIG_CNTL__CFG_VGA_RAM_EN_MASK 0x1
#define CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0
#define CONFIG_CNTL__VGA_DIS_MASK 0x2
#define CONFIG_CNTL__VGA_DIS__SHIFT 0x1
#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK 0x4
#define CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2
#define CONFIG_CNTL__GRPH_ADRSEL_MASK 0x18
#define CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3
#define CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK 0xffffffff
#define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0
#define CONFIG_F0_BASE__F0_BASE_MASK 0xffffffff
#define CONFIG_F0_BASE__F0_BASE__SHIFT 0x0
#define CONFIG_APER_SIZE__APER_SIZE_MASK 0xffffffff
#define CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0
#define CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK 0xfffff
#define CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0
#define BIF_SCRATCH0__BIF_SCRATCH0_MASK 0xffffffff
#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0
#define BIF_SCRATCH1__BIF_SCRATCH1_MASK 0xffffffff
#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0
#define BX_RESET_EN__COR_RESET_EN_MASK 0x1
#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0
#define BX_RESET_EN__REG_RESET_EN_MASK 0x2
#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1
#define BX_RESET_EN__STY_RESET_EN_MASK 0x4
#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2
#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK 0x7
#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0
#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x3
#define HW_DEBUG__HW_00_DEBUG_MASK 0x1
#define HW_DEBUG__HW_00_DEBUG__SHIFT 0x0
#define HW_DEBUG__HW_01_DEBUG_MASK 0x2
#define HW_DEBUG__HW_01_DEBUG__SHIFT 0x1
#define HW_DEBUG__HW_02_DEBUG_MASK 0x4
#define HW_DEBUG__HW_02_DEBUG__SHIFT 0x2
#define HW_DEBUG__HW_03_DEBUG_MASK 0x8
#define HW_DEBUG__HW_03_DEBUG__SHIFT 0x3
#define HW_DEBUG__HW_04_DEBUG_MASK 0x10
#define HW_DEBUG__HW_04_DEBUG__SHIFT 0x4
#define HW_DEBUG__HW_05_DEBUG_MASK 0x20
#define HW_DEBUG__HW_05_DEBUG__SHIFT 0x5
#define HW_DEBUG__HW_06_DEBUG_MASK 0x40
#define HW_DEBUG__HW_06_DEBUG__SHIFT 0x6
#define HW_DEBUG__HW_07_DEBUG_MASK 0x80
#define HW_DEBUG__HW_07_DEBUG__SHIFT 0x7
#define HW_DEBUG__HW_08_DEBUG_MASK 0x100
#define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
#define HW_DEBUG__HW_09_DEBUG_MASK 0x200Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.