drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h- Extension
.h- Size
- 4061 bytes
- Lines
- 57
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _clk_10_0_2_OFFSET_HEADER
#define _clk_10_0_2_OFFSET_HEADER
// addressBlock: clk_clk1_0_SmuClkDec
// base address: 0x5b800
#define mmCLK1_CLK_PLL_REQ 0x000f
#define mmCLK1_CLK_PLL_REQ_BASE_IDX 1
#define mmCLK1_CLK0_BYPASS_CNTL 0x0049
#define mmCLK1_CLK0_BYPASS_CNTL_BASE_IDX 1
#define mmCLK1_CLK1_BYPASS_CNTL 0x0053
#define mmCLK1_CLK1_BYPASS_CNTL_BASE_IDX 1
#define mmCLK1_CLK2_BYPASS_CNTL 0x005d
#define mmCLK1_CLK2_BYPASS_CNTL_BASE_IDX 1
#define mmCLK1_CLK2_STATUS 0x005e
#define mmCLK1_CLK2_STATUS_BASE_IDX 1
#define mmCLK1_CLK3_DFS_CNTL 0x005f
#define mmCLK1_CLK3_DFS_CNTL_BASE_IDX 1
#define mmCLK1_CLK3_DS_CNTL 0x0060
#define mmCLK1_CLK3_DS_CNTL_BASE_IDX 1
#define mmCLK1_CLK3_ALLOW_DS 0x0061
#define mmCLK1_CLK3_ALLOW_DS_BASE_IDX 1
#define mmCLK1_CLK3_BYPASS_CNTL 0x0067
#define mmCLK1_CLK3_BYPASS_CNTL_BASE_IDX 1
#define mmCLK1_CLK0_CURRENT_CNT 0x008a
#define mmCLK1_CLK0_CURRENT_CNT_BASE_IDX 1
#define mmCLK1_CLK1_CURRENT_CNT 0x008b
#define mmCLK1_CLK1_CURRENT_CNT_BASE_IDX 1
#define mmCLK1_CLK2_CURRENT_CNT 0x008c
#define mmCLK1_CLK2_CURRENT_CNT_BASE_IDX 1
#define mmCLK1_CLK3_CURRENT_CNT 0x008d
#define mmCLK1_CLK3_CURRENT_CNT_BASE_IDX 1
#endifAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.