drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_offset.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_offset.h

Extension

.h

Size

3629 bytes

Lines

51

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _clk_11_5_0_OFFSET_HEADER
#define _clk_11_5_0_OFFSET_HEADER


// addressBlock: clk_clk1_0_SmuClkDec
// base address: 0x5c000
#define mmCLK1_0_CLK1_CLK_PLL_REQ                                                                      0x0410
#define mmCLK1_0_CLK1_CLK_PLL_REQ_BASE_IDX                                                             0
#define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL                                                                 0x044a
#define mmCLK1_0_CLK1_CLK0_BYPASS_CNTL_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL                                                                 0x0454
#define mmCLK1_0_CLK1_CLK1_BYPASS_CNTL_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL                                                                 0x045e
#define mmCLK1_0_CLK1_CLK2_BYPASS_CNTL_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK3_DS_CNTL                                                                     0x0461
#define mmCLK1_0_CLK1_CLK3_DS_CNTL_BASE_IDX                                                            0
#define mmCLK1_0_CLK1_CLK3_ALLOW_DS                                                                    0x0462
#define mmCLK1_0_CLK1_CLK3_ALLOW_DS_BASE_IDX                                                           0
#define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL                                                                 0x0468
#define mmCLK1_0_CLK1_CLK3_BYPASS_CNTL_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK0_CURRENT_CNT                                                                 0x04a7
#define mmCLK1_0_CLK1_CLK0_CURRENT_CNT_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK1_CURRENT_CNT                                                                 0x04a8
#define mmCLK1_0_CLK1_CLK1_CURRENT_CNT_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK2_CURRENT_CNT                                                                 0x04a9
#define mmCLK1_0_CLK1_CLK2_CURRENT_CNT_BASE_IDX                                                        0
#define mmCLK1_0_CLK1_CLK3_CURRENT_CNT                                                                 0x04aa
#define mmCLK1_0_CLK1_CLK3_CURRENT_CNT_BASE_IDX                                                        0

#endif

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.