drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_5_0_sh_mask.h

Extension

.h

Size

5351 bytes

Lines

71

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _clk_11_5_0_SH_MASK_HEADER
#define _clk_11_5_0_SH_MASK_HEADER


// addressBlock: clk_clk1_0_SmuClkDec
//CLK1_0_CLK1_CLK_PLL_REQ
#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                            0x0
#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                           0x10
#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                              0x000001FFL
#define CLK1_0_CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                             0xFFFF0000L
//CLK1_0_CLK1_CLK0_BYPASS_CNTL
#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                  0x0
#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV__SHIFT                                                  0x10
#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                    0x00000007L
#define CLK1_0_CLK1_CLK0_BYPASS_CNTL__CLK0_BYPASS_DIV_MASK                                                    0x000F0000L
//CLK1_0_CLK1_CLK1_BYPASS_CNTL
#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                  0x0
#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV__SHIFT                                                  0x10
#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                    0x00000007L
#define CLK1_0_CLK1_CLK1_BYPASS_CNTL__CLK1_BYPASS_DIV_MASK                                                    0x000F0000L
//CLK1_0_CLK1_CLK2_BYPASS_CNTL
#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                  0x0
#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT                                                  0x10
#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                    0x00000007L
#define CLK1_0_CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK                                                    0x000F0000L
//CLK1_0_CLK1_CLK3_DS_CNTL
#define CLK1_0_CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                       0x0
#define CLK1_0_CLK1_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                         0x00000007L
//CLK1_0_CLK1_CLK3_ALLOW_DS
#define CLK1_0_CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS__SHIFT                                                       0x0
#define CLK1_0_CLK1_CLK3_ALLOW_DS__CLK3_ALLOW_DS_MASK                                                         0x00000001L
//CLK1_0_CLK1_CLK3_BYPASS_CNTL
#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                  0x0
#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV__SHIFT                                                  0x10
#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                    0x00000007L
#define CLK1_0_CLK1_CLK3_BYPASS_CNTL__CLK3_BYPASS_DIV_MASK                                                    0x000F0000L
//CLK1_0_CLK1_CLK0_CURRENT_CNT
#define CLK1_0_CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
#define CLK1_0_CLK1_CLK0_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
//CLK1_0_CLK1_CLK1_CURRENT_CNT
#define CLK1_0_CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
#define CLK1_0_CLK1_CLK1_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
//CLK1_0_CLK1_CLK2_CURRENT_CNT
#define CLK1_0_CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
#define CLK1_0_CLK1_CLK2_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL
//CLK1_0_CLK1_CLK3_CURRENT_CNT
#define CLK1_0_CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT__SHIFT                                                    0x0
#define CLK1_0_CLK1_CLK3_CURRENT_CNT__CURRENT_COUNT_MASK                                                      0xFFFFFFFFL

#endif

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.