drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h- Extension
.h- Size
- 3915 bytes
- Lines
- 45
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _clk_15_0_0_OFFSET_HEADER
#define _clk_15_0_0_OFFSET_HEADER
// addressBlock: clk_clk8_0_SmuClkDec
// base address: 0x6e000
#define regCLK8_CLK0_DS_CNTL 0x4c14
#define regCLK8_CLK0_DS_CNTL_BASE_IDX 0
#define regCLK8_CLK1_DS_CNTL 0x4c1c
#define regCLK8_CLK1_DS_CNTL_BASE_IDX 0
#define regCLK8_CLK2_DS_CNTL 0x4c24
#define regCLK8_CLK2_DS_CNTL_BASE_IDX 0
#define regCLK8_CLK3_DS_CNTL 0x4c2c
#define regCLK8_CLK3_DS_CNTL_BASE_IDX 0
#define regCLK8_CLK4_DS_CNTL 0x4c34
#define regCLK8_CLK4_DS_CNTL_BASE_IDX 0
#define regCLK8_CLK0_BYPASS_CNTL 0x4c1a
#define regCLK8_CLK0_BYPASS_CNTL_BASE_IDX 0
#define regCLK8_CLK1_BYPASS_CNTL 0x4c22
#define regCLK8_CLK1_BYPASS_CNTL_BASE_IDX 0
#define regCLK8_CLK2_BYPASS_CNTL 0x4c2a
#define regCLK8_CLK2_BYPASS_CNTL_BASE_IDX 0
#define regCLK8_CLK3_BYPASS_CNTL 0x4c32
#define regCLK8_CLK3_BYPASS_CNTL_BASE_IDX 0
#define regCLK8_CLK4_BYPASS_CNTL 0x4c3a
#define regCLK8_CLK4_BYPASS_CNTL_BASE_IDX 0
#define regCLK8_CLK_TICK_CNT_CONFIG_REG 0x4c51
#define regCLK8_CLK_TICK_CNT_CONFIG_REG_BASE_IDX 0
#define regCLK8_CLK_TICK_CNT_STATUS 0x4c52
#define regCLK8_CLK_TICK_CNT_STATUS_BASE_IDX 0
#define regCLK8_CLK0_CURRENT_CNT 0x4c53
#define regCLK8_CLK0_CURRENT_CNT_BASE_IDX 0
#define regCLK8_CLK1_CURRENT_CNT 0x4c54
#define regCLK8_CLK1_CURRENT_CNT_BASE_IDX 0
#define regCLK8_CLK2_CURRENT_CNT 0x4c55
#define regCLK8_CLK2_CURRENT_CNT_BASE_IDX 0
#define regCLK8_CLK3_CURRENT_CNT 0x4c56
#define regCLK8_CLK3_CURRENT_CNT_BASE_IDX 0
#define regCLK8_CLK4_CURRENT_CNT 0x4c57
#define regCLK8_CLK4_CURRENT_CNT_BASE_IDX 0
#endifAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.