drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_offset.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_offset.h

Extension

.h

Size

3717 bytes

Lines

43

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.

#ifndef _clk_15_0_5_OFFSET_HEADER
#define _clk_15_0_5_OFFSET_HEADER

// addressBlock: clk_clk5_0_SmuClkDec
// base address: 0x6c800
#define regCLK5_CLK0_DS_CNTL                                                                            0x4604
#define regCLK5_CLK0_DS_CNTL_BASE_IDX                                                                   0
#define regCLK5_CLK0_BYPASS_CNTL                                                                        0x460a
#define regCLK5_CLK0_BYPASS_CNTL_BASE_IDX                                                               0
#define regCLK5_CLK1_DS_CNTL                                                                            0x460c
#define regCLK5_CLK1_DS_CNTL_BASE_IDX                                                                   0
#define regCLK5_CLK1_BYPASS_CNTL                                                                        0x4612
#define regCLK5_CLK1_BYPASS_CNTL_BASE_IDX                                                               0
#define regCLK5_CLK2_DS_CNTL                                                                            0x4614
#define regCLK5_CLK2_DS_CNTL_BASE_IDX                                                                   0
#define regCLK5_CLK2_BYPASS_CNTL                                                                        0x461a
#define regCLK5_CLK2_BYPASS_CNTL_BASE_IDX                                                               0
#define regCLK5_CLK3_DS_CNTL                                                                            0x461c
#define regCLK5_CLK3_DS_CNTL_BASE_IDX                                                                   0
#define regCLK5_CLK3_BYPASS_CNTL                                                                        0x4622
#define regCLK5_CLK3_BYPASS_CNTL_BASE_IDX                                                               0
#define regCLK5_CLK_TICK_CNT_CONFIG_REG                                                                 0x4629
#define regCLK5_CLK_TICK_CNT_CONFIG_REG_BASE_IDX                                                        0
#define regCLK5_CLK_TICK_CNT_STATUS                                                                     0x462a
#define regCLK5_CLK_TICK_CNT_STATUS_BASE_IDX                                                            0
#define regCLK5_CLK0_CURRENT_CNT                                                                        0x462b
#define regCLK5_CLK0_CURRENT_CNT_BASE_IDX                                                               0
#define regCLK5_CLK1_CURRENT_CNT                                                                        0x462c
#define regCLK5_CLK1_CURRENT_CNT_BASE_IDX                                                               0
#define regCLK5_CLK2_CURRENT_CNT                                                                        0x462d
#define regCLK5_CLK2_CURRENT_CNT_BASE_IDX                                                               0
#define regCLK5_CLK3_CURRENT_CNT                                                                        0x462e
#define regCLK5_CLK3_CURRENT_CNT_BASE_IDX                                                               0
#define regCLK5_CLK4_CURRENT_CNT                                                                        0x462f
#define regCLK5_CLK4_CURRENT_CNT_BASE_IDX                                                               0
#define regCLK5_CLK5_CURRENT_CNT                                                                        0x4630
#define regCLK5_CLK5_CURRENT_CNT_BASE_IDX                                                               0

#endif

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.