drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_5_sh_mask.h

Extension

.h

Size

3498 bytes

Lines

46

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.

#ifndef _clk_15_0_5_SH_MASK_HEADER
#define _clk_15_0_5_SH_MASK_HEADER


// addressBlock: clk_clk5_0_SmuClkDec
//CLK5_CLK_TICK_CNT_CONFIG_REG
#define CLK5_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD__SHIFT                                                  0x0
#define CLK5_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD_MASK                                                    0x00FFFFFFL
//CLK5_CLK0_BYPASS_CNTL
#define CLK5_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT                                                         0x0
#define CLK5_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK                                                           0x00000007L
//CLK5_CLK1_BYPASS_CNTL
#define CLK5_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT                                                         0x0
#define CLK5_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK                                                           0x00000007L
//CLK5_CLK2_BYPASS_CNTL
#define CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT                                                         0x0
#define CLK5_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK                                                           0x00000007L
//CLK5_CLK3_BYPASS_CNTL
#define CLK5_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT                                                         0x0
#define CLK5_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK                                                           0x00000007L
//CLK5_CLK0_DS_CNTL
#define CLK5_CLK0_DS_CNTL__CLK0_DS_DIV_ID__SHIFT                                                              0x0
#define CLK5_CLK0_DS_CNTL__CLK0_DS_DIV_ID_MASK                                                                0x0000000FL
#define CLK5_CLK0_DS_CNTL__CLK0_ALLOW_DS__SHIFT                                                               0x4
#define CLK5_CLK0_DS_CNTL__CLK0_ALLOW_DS_MASK                                                                 0x00000010L
//CLK5_CLK1_DS_CNTL
#define CLK5_CLK1_DS_CNTL__CLK1_DS_DIV_ID__SHIFT                                                              0x0
#define CLK5_CLK1_DS_CNTL__CLK1_DS_DIV_ID_MASK                                                                0x0000000FL
#define CLK5_CLK1_DS_CNTL__CLK1_ALLOW_DS__SHIFT                                                               0x4
#define CLK5_CLK1_DS_CNTL__CLK1_ALLOW_DS_MASK                                                                 0x00000010L
//CLK5_CLK2_DS_CNTL
#define CLK5_CLK2_DS_CNTL__CLK2_DS_DIV_ID__SHIFT                                                              0x0
#define CLK5_CLK2_DS_CNTL__CLK2_DS_DIV_ID_MASK                                                                0x0000000FL
#define CLK5_CLK2_DS_CNTL__CLK2_ALLOW_DS__SHIFT                                                               0x4
#define CLK5_CLK2_DS_CNTL__CLK2_ALLOW_DS_MASK                                                                 0x00000010L
//CLK5_CLK3_DS_CNTL
#define CLK5_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT                                                              0x0
#define CLK5_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK                                                                0x0000000FL
#define CLK5_CLK3_DS_CNTL__CLK3_ALLOW_DS__SHIFT                                                               0x4
#define CLK5_CLK3_DS_CNTL__CLK3_ALLOW_DS_MASK                                                                 0x00000010L

#endif

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.