drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_enum.h
Extension
.h
Size
93563 bytes
Lines
1774
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef DCE_10_0_ENUM_H
#define DCE_10_0_ENUM_H

typedef enum DCIO_DC_GENERICA_SEL {
	DCIO_GENERICA_SEL_DACA_STEREOSYNC                = 0x0,
	DCIO_GENERICA_SEL_STEREOSYNC                     = 0x1,
	DCIO_GENERICA_SEL_DACA_PIXCLK                    = 0x2,
	DCIO_GENERICA_SEL_DACB_PIXCLK                    = 0x3,
	DCIO_GENERICA_SEL_DVOA_CTL3                      = 0x4,
	DCIO_GENERICA_SEL_P1_PLLCLK                      = 0x5,
	DCIO_GENERICA_SEL_P2_PLLCLK                      = 0x6,
	DCIO_GENERICA_SEL_DVOA_STEREOSYNC                = 0x7,
	DCIO_GENERICA_SEL_DACA_FIELD_NUMBER              = 0x8,
	DCIO_GENERICA_SEL_DACB_FIELD_NUMBER              = 0x9,
	DCIO_GENERICA_SEL_GENERICA_DCCG                  = 0xa,
	DCIO_GENERICA_SEL_SYNCEN                         = 0xb,
	DCIO_GENERICA_SEL_GENERICA_SCG                   = 0xc,
	DCIO_GENERICA_SEL_RESERVED_VALUE13               = 0xd,
	DCIO_GENERICA_SEL_RESERVED_VALUE14               = 0xe,
	DCIO_GENERICA_SEL_RESERVED_VALUE15               = 0xf,
	DCIO_GENERICA_SEL_GENERICA_DPRX                  = 0x10,
	DCIO_GENERICA_SEL_GENERICB_DPRX                  = 0x11,
} DCIO_DC_GENERICA_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
	DCIO_UNIPHYA_TEST_REFDIV_CLK                     = 0x0,
	DCIO_UNIPHYB_TEST_REFDIV_CLK                     = 0x1,
	DCIO_UNIPHYC_TEST_REFDIV_CLK                     = 0x2,
	DCIO_UNIPHYD_TEST_REFDIV_CLK                     = 0x3,
	DCIO_UNIPHYE_TEST_REFDIV_CLK                     = 0x4,
	DCIO_UNIPHYF_TEST_REFDIV_CLK                     = 0x5,
} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
	DCIO_UNIPHYA_FBDIV_CLK                           = 0x0,
	DCIO_UNIPHYB_FBDIV_CLK                           = 0x1,
	DCIO_UNIPHYC_FBDIV_CLK                           = 0x2,
	DCIO_UNIPHYD_FBDIV_CLK                           = 0x3,
	DCIO_UNIPHYE_FBDIV_CLK                           = 0x4,
	DCIO_UNIPHYF_FBDIV_CLK                           = 0x5,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
	DCIO_UNIPHYA_FBDIV_SSC_CLK                       = 0x0,
	DCIO_UNIPHYB_FBDIV_SSC_CLK                       = 0x1,
	DCIO_UNIPHYC_FBDIV_SSC_CLK                       = 0x2,
	DCIO_UNIPHYD_FBDIV_SSC_CLK                       = 0x3,
	DCIO_UNIPHYE_FBDIV_SSC_CLK                       = 0x4,
	DCIO_UNIPHYF_FBDIV_SSC_CLK                       = 0x5,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
	DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2                 = 0x0,
	DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2                 = 0x1,
	DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2                 = 0x2,
	DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2                 = 0x3,
	DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2                 = 0x4,
	DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2                 = 0x5,
} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
typedef enum DCIO_DC_GENERICB_SEL {
	DCIO_GENERICB_SEL_DACA_STEREOSYNC                = 0x0,
	DCIO_GENERICB_SEL_STEREOSYNC                     = 0x1,
	DCIO_GENERICB_SEL_DACA_PIXCLK                    = 0x2,
	DCIO_GENERICB_SEL_DACB_PIXCLK                    = 0x3,
	DCIO_GENERICB_SEL_DVOA_CTL3                      = 0x4,
	DCIO_GENERICB_SEL_P1_PLLCLK                      = 0x5,
	DCIO_GENERICB_SEL_P2_PLLCLK                      = 0x6,
	DCIO_GENERICB_SEL_DVOA_STEREOSYNC                = 0x7,
	DCIO_GENERICB_SEL_DACA_FIELD_NUMBER              = 0x8,
	DCIO_GENERICB_SEL_DACB_FIELD_NUMBER              = 0x9,
	DCIO_GENERICB_SEL_GENERICB_DCCG                  = 0xa,
	DCIO_GENERICB_SEL_SYNCEN                         = 0xb,
	DCIO_GENERICB_SEL_GENERICA_SCG                   = 0xc,
	DCIO_GENERICB_SEL_RESERVED_VALUE13               = 0xd,
	DCIO_GENERICB_SEL_RESERVED_VALUE14               = 0xe,
	DCIO_GENERICB_SEL_RESERVED_VALUE15               = 0xf,
} DCIO_DC_GENERICB_SEL;
typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
	DCIO_DC_PAD_EXTERN_SIG_SEL_MVP                   = 0x0,
	DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA                = 0x1,
	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK             = 0x2,
	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC           = 0x3,
	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA              = 0x4,
	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB              = 0x5,
	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC              = 0x6,
	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1                  = 0x7,
	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2                  = 0x8,
	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK               = 0x9,
	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA              = 0xa,
	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK               = 0xb,
	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA              = 0xc,
	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1                 = 0xd,
	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0                 = 0xe,
	DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL                = 0xf,

Annotation

Implementation Notes