drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_d.h- Extension
.h- Size
- 663601 bytes
- Lines
- 7659
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef DCE_11_0_D_H
#define DCE_11_0_D_H
#define mmPIPE0_PG_CONFIG 0x2c0
#define mmPIPE0_PG_ENABLE 0x2c1
#define mmPIPE0_PG_STATUS 0x2c2
#define mmPIPE1_PG_CONFIG 0x2c3
#define mmPIPE1_PG_ENABLE 0x2c4
#define mmPIPE1_PG_STATUS 0x2c5
#define mmPIPE2_PG_CONFIG 0x2c6
#define mmPIPE2_PG_ENABLE 0x2c7
#define mmPIPE2_PG_STATUS 0x2c8
#define mmDCFEV0_PG_CONFIG 0x2db
#define mmDCFEV0_PG_ENABLE 0x2dc
#define mmDCFEV0_PG_STATUS 0x2dd
#define mmDCPG_INTERRUPT_STATUS 0x2de
#define mmDCPG_INTERRUPT_CONTROL 0x2df
#define mmDC_IP_REQUEST_CNTL 0x2d2
#define mmDC_PGFSM_CONFIG_REG 0x2d3
#define mmDC_PGFSM_WRITE_REG 0x2d4
#define mmDC_PGCNTL_STATUS_REG 0x2d5
#define mmDCPG_TEST_DEBUG_INDEX 0x2d6
#define mmDCPG_TEST_DEBUG_DATA 0x2d7
#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628
#define mmBL1_PWM_USER_LEVEL 0x1629
#define mmBL1_PWM_TARGET_ABM_LEVEL 0x162a
#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162b
#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c
#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162d
#define mmBL1_PWM_ABM_CNTL 0x162e
#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162f
#define mmBL1_PWM_GRP2_REG_LOCK 0x1630
#define mmDC_ABM1_CNTL 0x1638
#define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639
#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163a
#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163b
#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163c
#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163d
#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163e
#define mmDC_ABM1_ACE_THRES_12 0x163f
#define mmDC_ABM1_ACE_THRES_34 0x1640
#define mmDC_ABM1_ACE_CNTL_MISC 0x1641
#define mmDC_ABM1_DEBUG_MISC 0x1649
#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164a
#define mmDC_ABM1_HG_MISC_CTRL 0x164b
#define mmDC_ABM1_LS_SUM_OF_LUMA 0x164c
#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164d
#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164e
#define mmDC_ABM1_LS_PIXEL_COUNT 0x164f
#define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650
#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651
#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652
#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653
#define mmDC_ABM1_HG_SAMPLE_RATE 0x1654
#define mmDC_ABM1_LS_SAMPLE_RATE 0x1655
#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656
#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657
#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658
#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659
#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165a
#define mmDC_ABM1_HG_RESULT_1 0x165b
#define mmDC_ABM1_HG_RESULT_2 0x165c
#define mmDC_ABM1_HG_RESULT_3 0x165d
#define mmDC_ABM1_HG_RESULT_4 0x165e
#define mmDC_ABM1_HG_RESULT_5 0x165f
#define mmDC_ABM1_HG_RESULT_6 0x1660
#define mmDC_ABM1_HG_RESULT_7 0x1661
#define mmDC_ABM1_HG_RESULT_8 0x1662
#define mmDC_ABM1_HG_RESULT_9 0x1663
#define mmDC_ABM1_HG_RESULT_10 0x1664
#define mmDC_ABM1_HG_RESULT_11 0x1665
#define mmDC_ABM1_HG_RESULT_12 0x1666
#define mmDC_ABM1_HG_RESULT_13 0x1667
#define mmDC_ABM1_HG_RESULT_14 0x1668
#define mmDC_ABM1_HG_RESULT_15 0x1669
#define mmDC_ABM1_HG_RESULT_16 0x166a
#define mmDC_ABM1_HG_RESULT_17 0x166b
#define mmDC_ABM1_HG_RESULT_18 0x166c
#define mmDC_ABM1_HG_RESULT_19 0x166d
#define mmDC_ABM1_HG_RESULT_20 0x166e
#define mmDC_ABM1_HG_RESULT_21 0x166f
#define mmDC_ABM1_HG_RESULT_22 0x1670
#define mmDC_ABM1_HG_RESULT_23 0x1671
#define mmDC_ABM1_HG_RESULT_24 0x1672
#define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169b
#define mmDC_ABM1_BL_MASTER_LOCK 0x169c
#define mmABM_TEST_DEBUG_INDEX 0x169e
#define mmABM_TEST_DEBUG_DATA 0x169f
#define mmCRTC_H_BLANK_EARLY_NUM 0x1b7d
#define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1b7dAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.