drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_offset.h- Extension
.h- Size
- 1872101 bytes
- Lines
- 18210
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _dce_12_0_OFFSET_HEADER
#define _dce_12_0_OFFSET_HEADER
// addressBlock: dce_dc_dispdec_VGA_MEM_WRITE_PAGE_ADDR
// base address: 0x48
#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
#define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
// addressBlock: dce_dc_dispdec_VGA_MEM_READ_PAGE_ADDR
// base address: 0x4c
#define mmdispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
#define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
// addressBlock: dce_dc_dc_perfmon0_dispdec
// base address: 0x0
#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0020
#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0022
#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL 0x0023
#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL2 0x0024
#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0025
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0026
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_HI 0x0027
#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_LOW 0x0028
#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dc_perfmon13_dispdec
// base address: 0x30
#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x002c
#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x002d
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x002e
#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CNTL 0x002f
#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CNTL2 0x0030
#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0031
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0032
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_HI 0x0033
#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_LOW 0x0034
#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dc_displaypllregs_dispdec
// base address: 0x0
#define mmPPLL_VREG_CFG 0x0038
#define mmPPLL_VREG_CFG_BASE_IDX 2
#define mmPPLL_MODE_CNTL 0x0039
#define mmPPLL_MODE_CNTL_BASE_IDX 2
#define mmPPLL_FREQ_CTRL0 0x003a
#define mmPPLL_FREQ_CTRL0_BASE_IDX 2
#define mmPPLL_FREQ_CTRL1 0x003b
#define mmPPLL_FREQ_CTRL1_BASE_IDX 2
#define mmPPLL_FREQ_CTRL2 0x003c
#define mmPPLL_FREQ_CTRL2_BASE_IDX 2
#define mmPPLL_FREQ_CTRL3 0x003d
#define mmPPLL_FREQ_CTRL3_BASE_IDX 2
#define mmPPLL_BW_CTRL_COARSE 0x003e
#define mmPPLL_BW_CTRL_COARSE_BASE_IDX 2
#define mmPPLL_BW_CTRL_FINE 0x0040
#define mmPPLL_BW_CTRL_FINE_BASE_IDX 2
#define mmPPLL_CAL_CTRL 0x0041
#define mmPPLL_CAL_CTRL_BASE_IDX 2
#define mmPPLL_LOOP_CTRL 0x0042
#define mmPPLL_LOOP_CTRL_BASE_IDX 2
#define mmPPLL_REFCLK_CNTL 0x0050
#define mmPPLL_REFCLK_CNTL_BASE_IDX 2
#define mmPPLL_CLKOUT_CNTL 0x0051
#define mmPPLL_CLKOUT_CNTL_BASE_IDX 2
#define mmPPLL_DFT_CNTL 0x0052
#define mmPPLL_DFT_CNTL_BASE_IDX 2
#define mmPPLL_ANALOG_CNTL 0x0053Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.