drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h- Extension
.h- Size
- 1408345 bytes
- Lines
- 14115
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _dcn_1_0_OFFSET_HEADER
#define _dcn_1_0_OFFSET_HEADER
// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x1300000
// addressBlock: dce_dc_hda_azendpoint_azdec
// base address: 0x1300000
// addressBlock: dce_dc_hda_azinputendpoint_azdec
// base address: 0x1300000
// addressBlock: dce_dc_hda_azroot_azdec
// base address: 0x1300000
// addressBlock: dce_dc_hda_azstream0_azdec
// base address: 0x1300000
// addressBlock: dce_dc_hda_azstream1_azdec
// base address: 0x1300020
// addressBlock: dce_dc_hda_azstream2_azdec
// base address: 0x1300040
// addressBlock: dce_dc_hda_azstream3_azdec
// base address: 0x1300060
// addressBlock: dce_dc_hda_azstream4_azdec
// base address: 0x1300080
// addressBlock: dce_dc_hda_azstream5_azdec
// base address: 0x13000a0
// addressBlock: dce_dc_hda_azstream6_azdec
// base address: 0x13000c0
// addressBlock: dce_dc_hda_azstream7_azdec
// base address: 0x13000e0
// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
// base address: 0x48
#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
// base address: 0x3b4
#define mmCRTC8_IDX 0x002d
#define mmCRTC8_IDX_BASE_IDX 1
#define mmCRTC8_DATA 0x002d
#define mmCRTC8_DATA_BASE_IDX 1
#define mmGENFC_WT 0x002e
#define mmGENFC_WT_BASE_IDX 1
#define mmGENS1 0x002e
#define mmGENS1_BASE_IDX 1
#define mmATTRDW 0x0030
#define mmATTRDW_BASE_IDX 1
#define mmATTRX 0x0030
#define mmATTRX_BASE_IDX 1
#define mmATTRDR 0x0030
#define mmATTRDR_BASE_IDX 1
#define mmGENMO_WT 0x0030
#define mmGENMO_WT_BASE_IDX 1
#define mmGENS0 0x0030
#define mmGENS0_BASE_IDX 1
#define mmGENENB 0x0030
#define mmGENENB_BASE_IDX 1
#define mmSEQ8_IDX 0x0031
#define mmSEQ8_IDX_BASE_IDX 1
#define mmSEQ8_DATA 0x0031
#define mmSEQ8_DATA_BASE_IDX 1
#define mmDAC_MASK 0x0031
#define mmDAC_MASK_BASE_IDX 1
#define mmDAC_R_INDEX 0x0031Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.