drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_1_offset.h- Extension
.h- Size
- 632888 bytes
- Lines
- 6194
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _dcn_2_0_1_OFFSET_HEADER
#define _dcn_2_0_1_OFFSET_HEADER
// addressBlock: dce_dc_dccg_dccg_dispdec
// base address: 0x0
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDP_DTO_DBUF_EN 0x0044
#define mmDP_DTO_DBUF_EN_BASE_IDX 1
#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmREFCLK_CNTL 0x0049
#define mmREFCLK_CNTL_BASE_IDX 1
#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL2 0x004e
#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
#define mmDCCG_DS_DTO_INCR 0x0053
#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
#define mmDCCG_DS_DTO_MODULO 0x0054
#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
#define mmDCCG_DS_CNTL 0x0055
#define mmDCCG_DS_CNTL_BASE_IDX 1
#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
#define mmDPREFCLK_CNTL 0x0058
#define mmDPREFCLK_CNTL_BASE_IDX 1
#define mmDCE_VERSION 0x005e
#define mmDCE_VERSION_BASE_IDX 1
#define mmDCCG_GTC_CNTL 0x0060
#define mmDCCG_GTC_CNTL_BASE_IDX 1
#define mmDCCG_GTC_DTO_INCR 0x0061
#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
#define mmDCCG_GTC_DTO_MODULO 0x0062
#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
#define mmDCCG_GTC_CURRENT 0x0063
#define mmDCCG_GTC_CURRENT_BASE_IDX 1
#define mmDSCCLK0_DTO_PARAM 0x006c
#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1
#define mmMILLISECOND_TIME_BASE_DIV 0x0070
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL 0x0073
#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL 0x0074
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_CAC_STATUS 0x0077
#define mmDCCG_CAC_STATUS_BASE_IDX 1
#define mmMICROSECOND_TIME_BASE_DIV 0x007b
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_DISP_CNTL_REG 0x007f
#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
#define mmOTG0_PIXEL_RATE_CNTL 0x0080
#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO0_PHASE 0x0081
#define mmDP_DTO0_PHASE_BASE_IDX 1
#define mmDP_DTO0_MODULO 0x0082
#define mmDP_DTO0_MODULO_BASE_IDX 1
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG1_PIXEL_RATE_CNTL 0x0084
#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO1_PHASE 0x0085
#define mmDP_DTO1_PHASE_BASE_IDX 1
#define mmDP_DTO1_MODULO 0x0086
#define mmDP_DTO1_MODULO_BASE_IDX 1
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDPPCLK0_DTO_PARAM 0x0099
#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK1_DTO_PARAM 0x009a
#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK2_DTO_PARAM 0x009b
#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.