drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_1_offset.h- Extension
.h- Size
- 1336648 bytes
- Lines
- 13272
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _dcn_3_0_1_OFFSET_HEADER
#define _dcn_3_0_1_OFFSET_HEADER
// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
// base address: 0x48
#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
// base address: 0x3b4
#define mmCRTC8_IDX 0x002d
#define mmCRTC8_IDX_BASE_IDX 1
#define mmCRTC8_DATA 0x002d
#define mmCRTC8_DATA_BASE_IDX 1
#define mmGENFC_WT 0x002e
#define mmGENFC_WT_BASE_IDX 1
#define mmGENS1 0x002e
#define mmGENS1_BASE_IDX 1
#define mmATTRDW 0x0030
#define mmATTRDW_BASE_IDX 1
#define mmATTRX 0x0030
#define mmATTRX_BASE_IDX 1
#define mmATTRDR 0x0030
#define mmATTRDR_BASE_IDX 1
#define mmGENMO_WT 0x0030
#define mmGENMO_WT_BASE_IDX 1
#define mmGENS0 0x0030
#define mmGENS0_BASE_IDX 1
#define mmGENENB 0x0030
#define mmGENENB_BASE_IDX 1
#define mmSEQ8_IDX 0x0031
#define mmSEQ8_IDX_BASE_IDX 1
#define mmSEQ8_DATA 0x0031
#define mmSEQ8_DATA_BASE_IDX 1
#define mmDAC_MASK 0x0031
#define mmDAC_MASK_BASE_IDX 1
#define mmDAC_R_INDEX 0x0031
#define mmDAC_R_INDEX_BASE_IDX 1
#define mmDAC_W_INDEX 0x0032
#define mmDAC_W_INDEX_BASE_IDX 1
#define mmDAC_DATA 0x0032
#define mmDAC_DATA_BASE_IDX 1
#define mmGENFC_RD 0x0032
#define mmGENFC_RD_BASE_IDX 1
#define mmGENMO_RD 0x0033
#define mmGENMO_RD_BASE_IDX 1
#define mmGRPH8_IDX 0x0033
#define mmGRPH8_IDX_BASE_IDX 1
#define mmGRPH8_DATA 0x0033
#define mmGRPH8_DATA_BASE_IDX 1
#define mmCRTC8_IDX_1 0x0035
#define mmCRTC8_IDX_1_BASE_IDX 1
#define mmCRTC8_DATA_1 0x0035
#define mmCRTC8_DATA_1_BASE_IDX 1
#define mmGENFC_WT_1 0x0036
#define mmGENFC_WT_1_BASE_IDX 1
#define mmGENS1_1 0x0036
#define mmGENS1_1_BASE_IDX 1
// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x0
#define mmCORB_WRITE_POINTER 0x0000
#define mmCORB_WRITE_POINTER_BASE_IDX 0
#define mmCORB_READ_POINTER 0x0000
#define mmCORB_READ_POINTER_BASE_IDX 0
#define mmCORB_CONTROL 0x0001
#define mmCORB_CONTROL_BASE_IDX 0
#define mmCORB_STATUS 0x0001
#define mmCORB_STATUS_BASE_IDX 0
#define mmCORB_SIZE 0x0001
#define mmCORB_SIZE_BASE_IDX 0
#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmRIRB_WRITE_POINTER 0x0004
#define mmRIRB_WRITE_POINTER_BASE_IDX 0
#define mmRESPONSE_INTERRUPT_COUNT 0x0004
#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
#define mmRIRB_CONTROL 0x0005
#define mmRIRB_CONTROL_BASE_IDX 0
#define mmRIRB_STATUS 0x0005
#define mmRIRB_STATUS_BASE_IDX 0
#define mmRIRB_SIZE 0x0005Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.