drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_4_offset.h- Extension
.h- Size
- 1555245 bytes
- Lines
- 15354
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _dcn_3_1_4_OFFSET_HEADER
#define _dcn_3_1_4_OFFSET_HEADER
// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x0
#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x0000
#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 0
#define regAZCONTROLLER0_CORB_READ_POINTER 0x0000
#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 0
#define regAZCONTROLLER0_CORB_CONTROL 0x0001
#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 0
#define regAZCONTROLLER0_CORB_STATUS 0x0001
#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 0
#define regAZCONTROLLER0_CORB_SIZE 0x0001
#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x0002
#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x0003
#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x0004
#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 0
#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x0004
#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_CONTROL 0x0005
#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_STATUS 0x0005
#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_SIZE 0x0005
#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x0008
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0
#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a
#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b
#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
// addressBlock: vga_vgaseqind
// base address: 0x0
#define ixSEQ00 0x0000
#define ixSEQ01 0x0001
#define ixSEQ02 0x0002
#define ixSEQ03 0x0003
#define ixSEQ04 0x0004
// addressBlock: vga_vgacrtind
// base address: 0x0
#define ixCRT00 0x0000
#define ixCRT01 0x0001
#define ixCRT02 0x0002
#define ixCRT03 0x0003
#define ixCRT04 0x0004
#define ixCRT05 0x0005
#define ixCRT06 0x0006
#define ixCRT07 0x0007
#define ixCRT08 0x0008
#define ixCRT09 0x0009
#define ixCRT0A 0x000a
#define ixCRT0B 0x000b
#define ixCRT0C 0x000c
#define ixCRT0D 0x000d
#define ixCRT0E 0x000e
#define ixCRT0F 0x000f
#define ixCRT10 0x0010
#define ixCRT11 0x0011
#define ixCRT12 0x0012
#define ixCRT13 0x0013
#define ixCRT14 0x0014
#define ixCRT15 0x0015
#define ixCRT16 0x0016
#define ixCRT17 0x0017
#define ixCRT18 0x0018
#define ixCRT1E 0x001e
#define ixCRT1F 0x001f
#define ixCRT22 0x0022
// addressBlock: vga_vgagrphind
// base address: 0x0Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.