drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h- Extension
.h- Size
- 1550434 bytes
- Lines
- 15307
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _dcn_3_1_5_OFFSET_HEADER
#define _dcn_3_1_5_OFFSET_HEADER
// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
// base address: 0x0
#define regDENTIST_DISPCLK_CNTL 0x0064
#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1
// addressBlock: dce_dc_dccg_dccg_dispdec
// base address: 0x0
#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regDP_DTO_DBUF_EN 0x0044
#define regDP_DTO_DBUF_EN_BASE_IDX 1
#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regDCCG_GATE_DISABLE_CNTL4 0x0049
#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1
#define regDPSTREAMCLK_CNTL 0x004a
#define regDPSTREAMCLK_CNTL_BASE_IDX 1
#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b
#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define regDCCG_PERFMON_CNTL2 0x004e
#define regDCCG_PERFMON_CNTL2_BASE_IDX 1
#define regDCCG_DS_DTO_INCR 0x0053
#define regDCCG_DS_DTO_INCR_BASE_IDX 1
#define regDCCG_DS_DTO_MODULO 0x0054
#define regDCCG_DS_DTO_MODULO_BASE_IDX 1
#define regDCCG_DS_CNTL 0x0055
#define regDCCG_DS_CNTL_BASE_IDX 1
#define regDCCG_DS_HW_CAL_INTERVAL 0x0056
#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
#define regDPREFCLK_CNTL 0x0058
#define regDPREFCLK_CNTL_BASE_IDX 1
#define regDCE_VERSION 0x005e
#define regDCE_VERSION_BASE_IDX 1
#define regDCCG_GTC_CNTL 0x0060
#define regDCCG_GTC_CNTL_BASE_IDX 1
#define regDCCG_GTC_DTO_INCR 0x0061
#define regDCCG_GTC_DTO_INCR_BASE_IDX 1
#define regDCCG_GTC_DTO_MODULO 0x0062
#define regDCCG_GTC_DTO_MODULO_BASE_IDX 1
#define regDCCG_GTC_CURRENT 0x0063
#define regDCCG_GTC_CURRENT_BASE_IDX 1
#define regSYMCLK32_SE_CNTL 0x0065
#define regSYMCLK32_SE_CNTL_BASE_IDX 1
#define regSYMCLK32_LE_CNTL 0x0066
#define regSYMCLK32_LE_CNTL_BASE_IDX 1
#define regDSCCLK0_DTO_PARAM 0x006c
#define regDSCCLK0_DTO_PARAM_BASE_IDX 1
#define regDSCCLK1_DTO_PARAM 0x006d
#define regDSCCLK1_DTO_PARAM_BASE_IDX 1
#define regDSCCLK2_DTO_PARAM 0x006e
#define regDSCCLK2_DTO_PARAM_BASE_IDX 1
#define regMILLISECOND_TIME_BASE_DIV 0x0070
#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071
#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
#define regDCCG_PERFMON_CNTL 0x0073
#define regDCCG_PERFMON_CNTL_BASE_IDX 1
#define regDCCG_GATE_DISABLE_CNTL 0x0074
#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075
#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076
#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regDCCG_CAC_STATUS 0x0077
#define regDCCG_CAC_STATUS_BASE_IDX 1
#define regMICROSECOND_TIME_BASE_DIV 0x007b
#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
#define regDCCG_GATE_DISABLE_CNTL2 0x007c
#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d
#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define regDCCG_DISP_CNTL_REG 0x007f
#define regDCCG_DISP_CNTL_REG_BASE_IDX 1
#define regOTG0_PIXEL_RATE_CNTL 0x0080Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.