drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_6_sh_mask.h

Extension

.h

Size

6736575 bytes

Lines

63274

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _dcn_3_1_6_SH_MASK_HEADER
#define _dcn_3_1_6_SH_MASK_HEADER


// addressBlock: dce_dc_hda_azcontroller_azdec
//AZCONTROLLER0_GLOBAL_CAPABILITIES
#define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT                            0x0
#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                        0x1
#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT                   0x3
#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT                           0x8
#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT                          0xc
#define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK                              0x0001L
#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                          0x0006L
#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK                     0x00F8L
#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK                             0x0F00L
#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK                            0xF000L
//AZCONTROLLER0_MINOR_VERSION
#define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION__SHIFT                                                     0x0
#define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION_MASK                                                       0xFFL
//AZCONTROLLER0_MAJOR_VERSION
#define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION__SHIFT                                                     0x0
#define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION_MASK                                                       0xFFL
//AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY
#define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                             0x0
#define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                               0xFFFFL
//AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY
#define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                               0x0
#define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                 0xFFFFL
//AZCONTROLLER0_GLOBAL_CONTROL
#define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT                                                 0x0
#define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT                                                    0x1
#define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT                               0x8
#define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET_MASK                                                   0x00000001L
#define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL_MASK                                                      0x00000002L
#define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK                                 0x00000100L
//AZCONTROLLER0_WAKE_ENABLE
#define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT                                               0x0
#define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK                                                 0x0001L
//AZCONTROLLER0_STATE_CHANGE_STATUS
#define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT                                         0x0
#define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK                                           0x0001L
//AZCONTROLLER0_GLOBAL_STATUS
#define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS__SHIFT                                                      0x1
#define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS_MASK                                                        0x00000002L
//AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY
#define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                     0x0
#define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                       0xFFFFL
//AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY
#define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                       0x0
#define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                         0xFFFFL
//AZCONTROLLER0_INTERRUPT_CONTROL
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT                                     0x0
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT                                     0x1
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT                                     0x2
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT                                     0x3
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT                                     0x4
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT                                     0x5
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT                                     0x6
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT                                     0x7
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT                                     0x8
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT                                     0x9
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT                                    0xa
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT                                    0xb
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT                                    0xc
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT                                    0xd
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT                                    0xe
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT                                    0xf
#define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT                                   0x1e
#define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT                                       0x1f
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK                                       0x00000001L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK                                       0x00000002L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK                                       0x00000004L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK                                       0x00000008L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK                                       0x00000010L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK                                       0x00000020L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK                                       0x00000040L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK                                       0x00000080L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK                                       0x00000100L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK                                       0x00000200L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK                                      0x00000400L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK                                      0x00000800L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK                                      0x00001000L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK                                      0x00002000L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK                                      0x00004000L
#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK                                      0x00008000L
#define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK                                     0x40000000L
#define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK                                         0x80000000L
//AZCONTROLLER0_INTERRUPT_STATUS
#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT                                      0x0
#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT                                      0x1

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.