drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_1_offset.h- Extension
.h- Size
- 1544947 bytes
- Lines
- 15260
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _dcn_3_5_1_OFFSET_HEADER
#define _dcn_3_5_1_OFFSET_HEADER
// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x1300000
#define regGLOBAL_CAPABILITIES 0x4b7000
#define regGLOBAL_CAPABILITIES_BASE_IDX 3
#define regMINOR_VERSION 0x4b7000
#define regMINOR_VERSION_BASE_IDX 3
#define regMAJOR_VERSION 0x4b7000
#define regMAJOR_VERSION_BASE_IDX 3
#define regOUTPUT_PAYLOAD_CAPABILITY 0x4b7001
#define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3
#define regINPUT_PAYLOAD_CAPABILITY 0x4b7001
#define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX 3
#define regGLOBAL_CONTROL 0x4b7002
#define regGLOBAL_CONTROL_BASE_IDX 3
#define regWAKE_ENABLE 0x4b7003
#define regWAKE_ENABLE_BASE_IDX 3
#define regSTATE_CHANGE_STATUS 0x4b7003
#define regSTATE_CHANGE_STATUS_BASE_IDX 3
#define regGLOBAL_STATUS 0x4b7004
#define regGLOBAL_STATUS_BASE_IDX 3
#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006
#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3
#define regINPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006
#define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3
#define regINTERRUPT_CONTROL 0x4b7008
#define regINTERRUPT_CONTROL_BASE_IDX 3
#define regINTERRUPT_STATUS 0x4b7009
#define regINTERRUPT_STATUS_BASE_IDX 3
#define regWALL_CLOCK_COUNTER 0x4b700c
#define regWALL_CLOCK_COUNTER_BASE_IDX 3
#define regSTREAM_SYNCHRONIZATION 0x4b700e
#define regSTREAM_SYNCHRONIZATION_BASE_IDX 3
#define regCORB_LOWER_BASE_ADDRESS 0x4b7010
#define regCORB_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regCORB_UPPER_BASE_ADDRESS 0x4b7011
#define regCORB_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x4b7012
#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 3
#define regAZCONTROLLER0_CORB_READ_POINTER 0x4b7012
#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 3
#define regAZCONTROLLER0_CORB_CONTROL 0x4b7013
#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 3
#define regAZCONTROLLER0_CORB_STATUS 0x4b7013
#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 3
#define regAZCONTROLLER0_CORB_SIZE 0x4b7013
#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 3
#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x4b7014
#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x4b7015
#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x4b7016
#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 3
#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x4b7016
#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3
#define regAZCONTROLLER0_RIRB_CONTROL 0x4b7017
#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 3
#define regAZCONTROLLER0_RIRB_STATUS 0x4b7017
#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 3
#define regAZCONTROLLER0_RIRB_SIZE 0x4b7017
#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 3
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3
#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019
#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x4b701a
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3
#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c
#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3
#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d
#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3
#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x4b780c
#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3
// addressBlock: azendpoint_sinkinfoind
// base address: 0x0
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
#define ixSINK_DESCRIPTION0 0x0005
#define ixSINK_DESCRIPTION1 0x0006
#define ixSINK_DESCRIPTION2 0x0007Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.