drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h- Extension
.h- Size
- 1782949 bytes
- Lines
- 17881
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _dcn_4_2_0_OFFSET_HEADER
#define _dcn_4_2_0_OFFSET_HEADER
// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x0
#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x0000
#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 0
#define regAZCONTROLLER0_CORB_READ_POINTER 0x0000
#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 0
#define regAZCONTROLLER0_CORB_CONTROL 0x0001
#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 0
#define regAZCONTROLLER0_CORB_STATUS 0x0001
#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 0
#define regAZCONTROLLER0_CORB_SIZE 0x0001
#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x0002
#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x0003
#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x0004
#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 0
#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x0004
#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_CONTROL 0x0005
#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_STATUS 0x0005
#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 0
#define regAZCONTROLLER0_RIRB_SIZE 0x0005
#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x0008
#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0
#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a
#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b
#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x074c
#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
// addressBlock: dc_perfmon_dc_perfmondebugind
// base address: 0x0
#define ixPERFMON_DEBUG_ID 0x0000
#define ixPERFMON_DEBUG01 0x0001
#define ixPERFMON_DEBUG02 0x0002
#define ixPERFMON_DEBUG03 0x0003
#define ixPERFMON_DEBUG04 0x0004
#define ixPERFMON_DEBUG05 0x0005
#define ixPERFMON_DEBUG06 0x0006
#define ixPERFMON_DEBUG07 0x0007
#define ixPERFMON_DEBUG08 0x0008
#define ixPERFMON_DEBUG09 0x0009
#define ixPERFMON_DEBUG0A 0x000a
#define ixPERFMON_DEBUG0B 0x000b
#define ixPERFMON_DEBUG0C 0x000c
#define ixPERFMON_DEBUG0D 0x000d
#define ixPERFMON_DEBUG0E 0x000e
#define ixPERFMON_DEBUG0F 0x000f
#define ixPERFMON_DEBUG10 0x0010
#define ixPERFMON_DEBUG11 0x0011
#define ixPERFMON_DEBUG12 0x0012
// addressBlock: mcif_wb0_mcif_wbdebugind
// base address: 0x0
#define ixMCIF_WB_DEBUG_ID 0x0000
#define ixID01_WB_FMT_DBG 0x0001
#define ixID02_WB_FMT_DBG 0x0002
#define ixID03_WB_FMT_DBG 0x0003
#define ixID04_WB_MGR_DBG 0x0004
#define ixID05_WB_MGR_DBG 0x0005
#define ixID06_WB_MGR_DBG 0x0006
#define ixID07_WB_MGR_DBG 0x0007
#define ixID08_WB_ARB_DBG 0x0008
#define ixID09_WB_ARB_DBG 0x0009
#define ixID0A_WB_ARB_DBG 0x000a
#define ixID0B_WB_ARB_DBG 0x000b
#define ixID0C_WB_ARB_DBG 0x000c
#define ixID0D_WB_ARB_DBG 0x000d
#define ixID0E_WB_ARB_DBG 0x000e
#define ixID0F_P010_WB_FMT_DBG_Y 0x000fAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.