drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_offset.h

Extension

.h

Size

1642 bytes

Lines

38

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _df_1_7_OFFSET_HEADER
#define _df_1_7_OFFSET_HEADER

#define mmFabricConfigAccessControl									0x0410
#define mmFabricConfigAccessControl_BASE_IDX								0

#define mmDF_PIE_AON0_DfGlobalClkGater									0x00fc
#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX								0

#define mmDF_CS_AON0_DramBaseAddress0									0x0044
#define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX								0

#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0								0x0214
#define mmDF_CS_AON0_CoherentSlaveModeCtrlA0_BASE_IDX							0


#endif

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.