drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/df/df_1_7_sh_mask.h

Extension

.h

Size

2745 bytes

Lines

53

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _df_1_7_SH_MASK_HEADER
#define _df_1_7_SH_MASK_HEADER

/* FabricConfigAccessControl */
#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT						0x0
#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT						0x1
#define FabricConfigAccessControl__CfgRegInstID__SHIFT							0x10
#define FabricConfigAccessControl__CfgRegInstAccEn_MASK							0x00000001L
#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK						0x00000002L
#define FabricConfigAccessControl__CfgRegInstID_MASK							0x00FF0000L

/* DF_PIE_AON0_DfGlobalClkGater */
#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT							0x0
#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK							0x0000000FL

/* DF_CS_AON0_DramBaseAddress0 */
#define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT							0x0
#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT						0x1
#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT						0x4
#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT						0x8
#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT						0xc
#define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK							0x00000001L
#define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK						0x00000002L
#define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK							0x000000F0L
#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK							0x00000700L
#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK							0xFFFFF000L

//DF_CS_AON0_CoherentSlaveModeCtrlA0
#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT					0x3
#define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK						0x00000008L

#endif

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.