drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_0_offset.h- Extension
.h- Size
- 61251 bytes
- Lines
- 648
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _dpcs_2_0_0_OFFSET_HEADER
#define _dpcs_2_0_0_OFFSET_HEADER
// addressBlock: dpcssys_dpcs0_dpcstx0_dispdec
// base address: 0x0
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL 0x2928
#define mmDPCSTX0_DPCSTX_TX_CLOCK_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_TX_CNTL 0x2929
#define mmDPCSTX0_DPCSTX_TX_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_CBUS_CNTL 0x292a
#define mmDPCSTX0_DPCSTX_CBUS_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL 0x292b
#define mmDPCSTX0_DPCSTX_INTERRUPT_CNTL_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR 0x292c
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA 0x292d
#define mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG 0x292e
#define mmDPCSTX0_DPCSTX_DEBUG_CONFIG_BASE_IDX 2
// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
// base address: 0x0
#define mmRDPCSTX0_RDPCSTX_CNTL 0x2930
#define mmRDPCSTX0_RDPCSTX_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL 0x2931
#define mmRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL 0x2932
#define mmRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA 0x2933
#define mmRDPCSTX0_RDPCSTX_PLL_UPDATE_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR 0x2934
#define mmRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_CR_DATA 0x2935
#define mmRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX 2
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL 0x2936
#define mmRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL 0x2937
#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL2 0x2938
#define mmRDPCSTX0_RDPCSTX_MEM_POWER_CTRL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_SCRATCH 0x2939
#define mmRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG 0x293c
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG 0x293d
#define mmRDPCSTX0_RDPCSTX_DEBUG_CONFIG_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0 0x2940
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1 0x2941
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2 0x2942
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3 0x2943
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4 0x2944
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5 0x2945
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6 0x2946
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7 0x2947
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8 0x2948
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9 0x2949
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10 0x294a
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11 0x294b
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12 0x294c
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13 0x294d
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14 0x294e
#define mmRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0 0x294f
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1 0x2950
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2 0x2951
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3 0x2952
#define mmRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL 0x2953
#define mmRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX 2
#define mmRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3 0x2954Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.