drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_1_4_offset.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_1_4_offset.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_1_4_offset.h
Extension: .h
Size: 782975 bytes
Lines: 7216
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _dpcs_3_1_4_OFFSET_HEADER
#define _dpcs_3_1_4_OFFSET_HEADER



// addressBlock: dpcssys_cr0_rdpcstxcrind
// base address: 0x0
#define ixDPCSSYS_CR0_SUP_DIG_IDCODE_LO                                                                0x0000
#define ixDPCSSYS_CR0_SUP_DIG_IDCODE_HI                                                                0x0001
#define ixDPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
#define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN                                                              0x001f
#define ixDPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
#define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
#define ixDPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN                                                              0x0022
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
#define ixDPCSSYS_CR0_SUP_DIG_ASIC_IN                                                                  0x0036
#define ixDPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN                                                              0x0037
#define ixDPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
#define ixDPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL                                                           0x0040
#define ixDPCSSYS_CR0_SUP_ANA_RTUNE_CTRL                                                               0x0041
#define ixDPCSSYS_CR0_SUP_ANA_BG1                                                                      0x0042
#define ixDPCSSYS_CR0_SUP_ANA_BG2                                                                      0x0043
#define ixDPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074

Annotation

Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.