drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_1_4_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_3_1_4_sh_mask.h

Extension

.h

Size

5931549 bytes

Lines

55195

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _dpcs_3_1_4_SH_MASK_HEADER
#define _dpcs_3_1_4_SH_MASK_HEADER


// addressBlock: dpcssys_cr0_rdpcstxcrind
//DPCSSYS_CR0_SUP_DIG_IDCODE_LO
//DPCSSYS_CR0_SUP_DIG_IDCODE_HI
//DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x7
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0x8
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0x9
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xa
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xb
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xc
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xd
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x0001L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x0004L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x0070L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x0080L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x0100L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x0200L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x0400L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x0800L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x1000L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x2000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.