drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_1_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_1_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_1_offset.h- Extension
.h- Size
- 10302 bytes
- Lines
- 110
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: MIT
// Copyright (c) 2026 Advanced Micro Devices, Inc. All rights reserved.
#ifndef _dpcs_4_0_1_OFFSET_HEADER
#define _dpcs_4_0_1_OFFSET_HEADER
// addressBlock: dpcssys_dcio_dcio_dispdec
// base address: 0x0
#define regDC_GENERICA 0x2868
#define regDC_GENERICA_BASE_IDX 2
#define regDC_GENERICB 0x2869
#define regDC_GENERICB_BASE_IDX 2
#define regDCIO_CLOCK_CNTL 0x286a
#define regDCIO_CLOCK_CNTL_BASE_IDX 2
#define regDC_REF_CLK_CNTL 0x286b
#define regDC_REF_CLK_CNTL_BASE_IDX 2
#define regUNIPHYA_LINK_CNTL 0x286d
#define regUNIPHYA_LINK_CNTL_BASE_IDX 2
#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYB_LINK_CNTL 0x286f
#define regUNIPHYB_LINK_CNTL_BASE_IDX 2
#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYC_LINK_CNTL 0x2871
#define regUNIPHYC_LINK_CNTL_BASE_IDX 2
#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYD_LINK_CNTL 0x2873
#define regUNIPHYD_LINK_CNTL_BASE_IDX 2
#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regUNIPHYE_LINK_CNTL 0x2875
#define regUNIPHYE_LINK_CNTL_BASE_IDX 2
#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define regDCIO_WRCMD_DELAY 0x287e
#define regDCIO_WRCMD_DELAY_BASE_IDX 2
#define regDC_PINSTRAPS 0x2880
#define regDC_PINSTRAPS_BASE_IDX 2
#define regDCIO_SPARE 0x2882
#define regDCIO_SPARE_BASE_IDX 2
#define regINTERCEPT_STATE 0x2884
#define regINTERCEPT_STATE_BASE_IDX 2
#define regDCIO_PATTERN_GEN_PAT 0x2886
#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2
#define regDCIO_PATTERN_GEN_EN 0x2887
#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b
#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2
#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c
#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
#define regDPCS_DCIO_TEST_CLK_SRC 0x2890
#define regDPCS_DCIO_TEST_CLK_SRC_BASE_IDX 2
#define regDCIO_DEBUG 0x2897
#define regDCIO_DEBUG_BASE_IDX 2
#define regDCIO_TEST_DEBUG_INDEX 0x2899
#define regDCIO_TEST_DEBUG_INDEX_BASE_IDX 2
#define regDCIO_TEST_DEBUG_DATA 0x289a
#define regDCIO_TEST_DEBUG_DATA_BASE_IDX 2
#define regDBG_OUT_CNTL 0x289c
#define regDBG_OUT_CNTL_BASE_IDX 2
#define regDCIO_DEBUG_CONFIG 0x289d
#define regDCIO_DEBUG_CONFIG_BASE_IDX 2
#define regDCIO_SOFT_RESET 0x289e
#define regDCIO_SOFT_RESET_BASE_IDX 2
// addressBlock: dpcssys_dcio_dcio_chip_dispdec
// base address: 0x0
#define regDC_GPIO_DDC1_MASK 0x28d0
#define regDC_GPIO_DDC1_MASK_BASE_IDX 2
#define regDC_GPIO_DDC2_MASK 0x28d4
#define regDC_GPIO_DDC2_MASK_BASE_IDX 2
#define regDC_GPIO_DDC3_MASK 0x28d8
#define regDC_GPIO_DDC3_MASK_BASE_IDX 2
#define regDC_GPIO_DDCVGA_MASK 0x28e8
#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2
#define regDC_GPIO_DDCVGA_A 0x28e9
#define regDC_GPIO_DDCVGA_A_BASE_IDX 2
#define regDC_GPIO_DDCVGA_EN 0x28ea
#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2
#define regDC_GPIO_DDCVGA_Y 0x28eb
#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2
#define regDC_GPIO_PWRSEQ0_EN 0x28fa
#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.