drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h- Extension
.h- Size
- 1304883 bytes
- Lines
- 11974
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _dpcs_4_2_0_OFFSET_HEADER
#define _dpcs_4_2_0_OFFSET_HEADER
// addressBlock: dpcssys_dpcssys_cr0_dispdec
// base address: 0x0
#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX 2
#define regDPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
#define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr1_dispdec
// base address: 0x360
#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX 2
#define regDPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
#define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr2_dispdec
// base address: 0x6c0
#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX 2
#define regDPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
#define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr3_dispdec
// base address: 0xa20
#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR 0x2bbc
#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX 2
#define regDPCSSYS_CR3_DPCSSYS_CR_DATA 0x2bbd
#define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_dpcssys_cr4_dispdec
// base address: 0xd80
#define regDPCSSYS_CR4_DPCSSYS_CR_ADDR 0x2c94
#define regDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX 2
#define regDPCSSYS_CR4_DPCSSYS_CR_DATA 0x2c95
#define regDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX 2
// addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec
// base address: 0x0
#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN 0x2f10
#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX 2
#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL 0x2f11
#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2
#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK 0x2f12
#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2
#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y 0x2f13
#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2
#define regPWRSEQ0_PANEL_PWRSEQ_CNTL 0x2f14
#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX 2
#define regPWRSEQ0_PANEL_PWRSEQ_STATE 0x2f15
#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX 2
#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1 0x2f16
#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX 2
#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2 0x2f17
#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX 2
#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1 0x2f18
#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX 2
#define regPWRSEQ0_BL_PWM_CNTL 0x2f19
#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX 2
#define regPWRSEQ0_BL_PWM_CNTL2 0x2f1a
#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX 2
#define regPWRSEQ0_BL_PWM_PERIOD_CNTL 0x2f1b
#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX 2
#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK 0x2f1c
#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX 2
#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2 0x2f1d
#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX 2
#define regPWRSEQ0_PWRSEQ_SPARE 0x2f21
#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX 2
// addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec
// base address: 0x1b0
#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN 0x2f7c
#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX 2
#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL 0x2f7d
#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX 2
#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK 0x2f7e
#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX 2
#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y 0x2f7f
#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX 2
#define regPWRSEQ1_PANEL_PWRSEQ_CNTL 0x2f80Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.