drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h- Extension
.h- Size
- 4645520 bytes
- Lines
- 44166
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_10_1_0_SH_MASK_HEADER
#define _gc_10_1_0_SH_MASK_HEADER
// addressBlock: gc_sdma0_sdma0dec
//SDMA0_DEC_START
#define SDMA0_DEC_START__START__SHIFT 0x0
#define SDMA0_DEC_START__START_MASK 0xFFFFFFFFL
//SDMA0_PG_CNTL
#define SDMA0_PG_CNTL__CMD__SHIFT 0x0
#define SDMA0_PG_CNTL__STATUS__SHIFT 0x10
#define SDMA0_PG_CNTL__CMD_MASK 0x0000000FL
#define SDMA0_PG_CNTL__STATUS_MASK 0x000F0000L
//SDMA0_PG_CTX_LO
#define SDMA0_PG_CTX_LO__ADDR__SHIFT 0x0
#define SDMA0_PG_CTX_LO__ADDR_MASK 0xFFFFFFFFL
//SDMA0_PG_CTX_HI
#define SDMA0_PG_CTX_HI__ADDR__SHIFT 0x0
#define SDMA0_PG_CTX_HI__ADDR_MASK 0xFFFFFFFFL
//SDMA0_PG_CTX_CNTL
#define SDMA0_PG_CTX_CNTL__VMID__SHIFT 0x0
#define SDMA0_PG_CTX_CNTL__VMID_MASK 0x0000000FL
//SDMA0_POWER_CNTL
#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0
#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1
#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3
#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8
#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9
#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa
#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb
#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc
#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a
#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L
#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L
#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L
#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L
#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L
#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L
#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L
#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
//SDMA0_CLK_CTRL
#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc
#define SDMA0_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN__SHIFT 0x17
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
#define SDMA0_CLK_CTRL__RESERVED_MASK 0x007FF000L
#define SDMA0_CLK_CTRL__UTCL1_FORCE_INV_RET_FIFO_FULL_EN_MASK 0x00800000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L
#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L
//SDMA0_CNTL
#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1
#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
#define SDMA0_CNTL__PAGE_INT_ENABLE__SHIFT 0x7
#define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10
#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12
#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L
#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L
#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
#define SDMA0_CNTL__PAGE_INT_ENABLE_MASK 0x00000080L
#define SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000LAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.