drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_default.h- Extension
.h- Size
- 649495 bytes
- Lines
- 7276
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_10_3_0_DEFAULT_HEADER
#define _gc_10_3_0_DEFAULT_HEADER
// addressBlock: gc_sdma0_sdma0dec
#define mmSDMA0_DEC_START_DEFAULT 0x00000000
#define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
#define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
#define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
#define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
#define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
#define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
#define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
#define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
#define mmSDMA0_CNTL_DEFAULT 0x000000c2
#define mmSDMA0_CHICKEN_BITS_DEFAULT 0x03ef0107
#define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000444
#define mmSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000444
#define mmSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
#define mmSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
#define mmSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000
#define mmSDMA0_PROGRAM_DEFAULT 0x00000000
#define mmSDMA0_STATUS_REG_DEFAULT 0x46dee557
#define mmSDMA0_STATUS1_REG_DEFAULT 0x000003ff
#define mmSDMA0_RD_BURST_CNTL_DEFAULT 0x00000002
#define mmSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000
#define mmSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000
#define mmSDMA0_F32_CNTL_DEFAULT 0x00000001
#define mmSDMA0_FREEZE_DEFAULT 0x00000000
#define mmSDMA0_PHASE0_QUANTUM_DEFAULT 0x00010002
#define mmSDMA0_PHASE1_QUANTUM_DEFAULT 0x00010002
#define mmSDMA0_EDC_CONFIG_DEFAULT 0x00000002
#define mmSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff
#define mmSDMA0_ID_DEFAULT 0x00000001
#define mmSDMA0_VERSION_DEFAULT 0x00000500
#define mmSDMA0_EDC_COUNTER_DEFAULT 0x00000000
#define mmSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
#define mmSDMA0_STATUS2_REG_DEFAULT 0x00000000
#define mmSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200
#define mmSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000
#define mmSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000
#define mmSDMA0_UTCL1_CNTL_DEFAULT 0xd0000191
#define mmSDMA0_UTCL1_WATERMK_DEFAULT 0xfffbd9fb
#define mmSDMA0_UTCL1_RD_STATUS_DEFAULT 0x01011555
#define mmSDMA0_UTCL1_WR_STATUS_DEFAULT 0x51011555
#define mmSDMA0_UTCL1_INV0_DEFAULT 0x00000800
#define mmSDMA0_UTCL1_INV1_DEFAULT 0x00000000
#define mmSDMA0_UTCL1_INV2_DEFAULT 0x00000000
#define mmSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000
#define mmSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000
#define mmSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000
#define mmSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000
#define mmSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00000000
#define mmSDMA0_UTCL1_PAGE_DEFAULT 0x010cec00
#define mmSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000006
#define mmSDMA0_CHICKEN_BITS_2_DEFAULT 0x00100007
#define mmSDMA0_STATUS3_REG_DEFAULT 0x03f00000
#define mmSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
#define mmSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
#define mmSDMA0_PHASE2_QUANTUM_DEFAULT 0x00010002
#define mmSDMA0_ERROR_LOG_DEFAULT 0x0000000f
#define mmSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000
#define mmSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000
#define mmSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000
#define mmSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000
#define mmSDMA0_F32_COUNTER_DEFAULT 0x00000000
#define mmSDMA0_CRD_CNTL_DEFAULT 0x1850c640
#define mmSDMA0_AQL_STATUS_DEFAULT 0x00000003
#define mmSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x00000000
#define mmSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
#define mmSDMA0_TLBI_GCR_CNTL_DEFAULT 0x40180454
#define mmSDMA0_TILING_CONFIG_DEFAULT 0x00000000
#define mmSDMA0_INT_STATUS_DEFAULT 0x00000000
#define mmSDMA0_HOLE_ADDR_LO_DEFAULT 0x00000000
#define mmSDMA0_HOLE_ADDR_HI_DEFAULT 0x00000000
#define mmSDMA0_CLOCK_GATING_REG_DEFAULT 0x00000000
#define mmSDMA0_STATUS4_REG_DEFAULT 0x00000001
#define mmSDMA0_SCRATCH_RAM_DATA_DEFAULT 0x00000000
#define mmSDMA0_SCRATCH_RAM_ADDR_DEFAULT 0x00000000
#define mmSDMA0_TIMESTAMP_CNTL_DEFAULT 0x00000000
#define mmSDMA0_STATUS5_REG_DEFAULT 0x00000000
#define mmSDMA0_QUEUE_RESET_REQ_DEFAULT 0x00000000
#define mmSDMA0_GFX_RB_CNTL_DEFAULT 0x80840000
#define mmSDMA0_GFX_RB_BASE_DEFAULT 0x00000000
#define mmSDMA0_GFX_RB_BASE_HI_DEFAULT 0x00000000
#define mmSDMA0_GFX_RB_RPTR_DEFAULT 0x00000000
#define mmSDMA0_GFX_RB_RPTR_HI_DEFAULT 0x00000000
#define mmSDMA0_GFX_RB_WPTR_DEFAULT 0x00000000
#define mmSDMA0_GFX_RB_WPTR_HI_DEFAULT 0x00000000Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.