drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_default.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_default.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_default.h- Extension
.h- Size
- 546818 bytes
- Lines
- 6115
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_11_0_0_DEFAULT_HEADER
#define _gc_11_0_0_DEFAULT_HEADER
// addressBlock: gc_sdma0_sdma0dec
#define regSDMA0_DEC_START_DEFAULT 0x00000000
#define regSDMA0_F32_MISC_CNTL_DEFAULT 0x00000000
#define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
#define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
#define regSDMA0_POWER_CNTL_DEFAULT 0x00000000
#define regSDMA0_CNTL_DEFAULT 0x00002440
#define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d186
#define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000545
#define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545
#define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
#define regSDMA0_RB_RPTR_FETCH_HI_DEFAULT 0x00000000
#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_DEFAULT 0x00000000
#define regSDMA0_IB_OFFSET_FETCH_DEFAULT 0x00000000
#define regSDMA0_PROGRAM_DEFAULT 0x00000000
#define regSDMA0_STATUS_REG_DEFAULT 0x46dee557
#define regSDMA0_STATUS1_REG_DEFAULT 0x000403ff
#define regSDMA0_CNTL1_DEFAULT 0x00000c30
#define regSDMA0_HBM_PAGE_CONFIG_DEFAULT 0x00000000
#define regSDMA0_UCODE_CHECKSUM_DEFAULT 0x00000000
#define regSDMA0_FREEZE_DEFAULT 0x00000000
#define regSDMA0_PROCESS_QUANTUM0_DEFAULT 0x00000000
#define regSDMA0_PROCESS_QUANTUM1_DEFAULT 0x00000000
#define regSDMA0_WATCHDOG_CNTL_DEFAULT 0x00000000
#define regSDMA0_QUEUE_STATUS0_DEFAULT 0x22222222
#define regSDMA0_EDC_CONFIG_DEFAULT 0x00000004
#define regSDMA0_BA_THRESHOLD_DEFAULT 0x03ff03ff
#define regSDMA0_ID_DEFAULT 0x00000001
#define regSDMA0_VERSION_DEFAULT 0x00000600
#define regSDMA0_EDC_COUNTER_DEFAULT 0x00000000
#define regSDMA0_EDC_COUNTER_CLEAR_DEFAULT 0x00000000
#define regSDMA0_STATUS2_REG_DEFAULT 0x00000000
#define regSDMA0_ATOMIC_CNTL_DEFAULT 0x00000200
#define regSDMA0_ATOMIC_PREOP_LO_DEFAULT 0x00000000
#define regSDMA0_ATOMIC_PREOP_HI_DEFAULT 0x00000000
#define regSDMA0_UTCL1_CNTL_DEFAULT 0x2c000288
#define regSDMA0_UTCL1_WATERMK_DEFAULT 0x00000000
#define regSDMA0_UTCL1_TIMEOUT_DEFAULT 0x00000000
#define regSDMA0_UTCL1_PAGE_DEFAULT 0x010cec00
#define regSDMA0_UTCL1_RD_STATUS_DEFAULT 0xb90700ff
#define regSDMA0_UTCL1_WR_STATUS_DEFAULT 0xf90780ff
#define regSDMA0_UTCL1_INV0_DEFAULT 0x00000000
#define regSDMA0_UTCL1_INV1_DEFAULT 0x00000000
#define regSDMA0_UTCL1_INV2_DEFAULT 0x00000000
#define regSDMA0_UTCL1_RD_XNACK0_DEFAULT 0x00000000
#define regSDMA0_UTCL1_RD_XNACK1_DEFAULT 0x00000000
#define regSDMA0_UTCL1_WR_XNACK0_DEFAULT 0x00000000
#define regSDMA0_UTCL1_WR_XNACK1_DEFAULT 0x00000000
#define regSDMA0_RELAX_ORDERING_LUT_DEFAULT 0xc0000806
#define regSDMA0_CHICKEN_BITS_2_DEFAULT 0x400007c9
#define regSDMA0_STATUS3_REG_DEFAULT 0x03f00000
#define regSDMA0_PHYSICAL_ADDR_LO_DEFAULT 0x00000000
#define regSDMA0_PHYSICAL_ADDR_HI_DEFAULT 0x00000000
#define regSDMA0_GLOBAL_QUANTUM_DEFAULT 0x00000000
#define regSDMA0_ERROR_LOG_DEFAULT 0x0000000f
#define regSDMA0_PUB_DUMMY_REG0_DEFAULT 0x00000000
#define regSDMA0_PUB_DUMMY_REG1_DEFAULT 0x00000000
#define regSDMA0_PUB_DUMMY_REG2_DEFAULT 0x00000000
#define regSDMA0_PUB_DUMMY_REG3_DEFAULT 0x00000000
#define regSDMA0_F32_COUNTER_DEFAULT 0x00000000
#define regSDMA0_CRD_CNTL_DEFAULT 0x18694840
#define regSDMA0_RLC_CGCG_CTRL_DEFAULT 0x00400000
#define regSDMA0_AQL_STATUS_DEFAULT 0x00000003
#define regSDMA0_EA_DBIT_ADDR_DATA_DEFAULT 0x0000270d
#define regSDMA0_EA_DBIT_ADDR_INDEX_DEFAULT 0x00000000
#define regSDMA0_TLBI_GCR_CNTL_DEFAULT 0x40600454
#define regSDMA0_TILING_CONFIG_DEFAULT 0x00000000
#define regSDMA0_INT_STATUS_DEFAULT 0x00000000
#define regSDMA0_HOLE_ADDR_LO_DEFAULT 0x00000000
#define regSDMA0_HOLE_ADDR_HI_DEFAULT 0x00000000
#define regSDMA0_CLOCK_GATING_STATUS_DEFAULT 0x00000000
#define regSDMA0_STATUS4_REG_DEFAULT 0x00000001
#define regSDMA0_SCRATCH_RAM_DATA_DEFAULT 0x00000000
#define regSDMA0_SCRATCH_RAM_ADDR_DEFAULT 0x00000000
#define regSDMA0_TIMESTAMP_CNTL_DEFAULT 0x00000000
#define regSDMA0_STATUS5_REG_DEFAULT 0x00000000
#define regSDMA0_QUEUE_RESET_REQ_DEFAULT 0x00000000
#define regSDMA0_STATUS6_REG_DEFAULT 0x00000000
#define regSDMA0_UCODE1_CHECKSUM_DEFAULT 0x00000000
#define regSDMA0_CE_CTRL_DEFAULT 0x00000000
#define regSDMA0_FED_STATUS_DEFAULT 0x00000000
#define regSDMA0_QUEUE0_RB_CNTL_DEFAULT 0x00040800
#define regSDMA0_QUEUE0_RB_BASE_DEFAULT 0x00000000
#define regSDMA0_QUEUE0_RB_BASE_HI_DEFAULT 0x00000000
#define regSDMA0_QUEUE0_RB_RPTR_DEFAULT 0x00000000
#define regSDMA0_QUEUE0_RB_RPTR_HI_DEFAULT 0x00000000Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.