drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h- Extension
.h- Size
- 4345221 bytes
- Lines
- 41665
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_11_0_0_SH_MASK_HEADER
#define _gc_11_0_0_SH_MASK_HEADER
// addressBlock: gc_sdma0_sdma0dec
//SDMA0_DEC_START
#define SDMA0_DEC_START__START__SHIFT 0x0
#define SDMA0_DEC_START__START_MASK 0xFFFFFFFFL
//SDMA0_F32_MISC_CNTL
#define SDMA0_F32_MISC_CNTL__F32_WAKEUP__SHIFT 0x0
#define SDMA0_F32_MISC_CNTL__F32_WAKEUP_MASK 0x00000001L
//SDMA0_GLOBAL_TIMESTAMP_LO
#define SDMA0_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0
#define SDMA0_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL
//SDMA0_GLOBAL_TIMESTAMP_HI
#define SDMA0_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0
#define SDMA0_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL
//SDMA0_POWER_CNTL
#define SDMA0_POWER_CNTL__LS_ENABLE__SHIFT 0x8
#define SDMA0_POWER_CNTL__LS_ENABLE_MASK 0x00000100L
//SDMA0_CNTL
#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0
#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3
#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4
#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5
#define SDMA0_CNTL__PIO_DONE_ACK_ENABLE__SHIFT 0x6
#define SDMA0_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8
#define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9
#define SDMA0_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa
#define SDMA0_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb
#define SDMA0_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc
#define SDMA0_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd
#define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10
#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11
#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c
#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d
#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e
#define SDMA0_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f
#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L
#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L
#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L
#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L
#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L
#define SDMA0_CNTL__PIO_DONE_ACK_ENABLE_MASK 0x00000040L
#define SDMA0_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L
#define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L
#define SDMA0_CNTL__CP_MES_INT_ENABLE_MASK 0x00000400L
#define SDMA0_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L
#define SDMA0_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L
#define SDMA0_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L
#define SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L
#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L
#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L
#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L
#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L
#define SDMA0_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L
//SDMA0_CHICKEN_BITS
#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2
#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x5
#define SDMA0_CHICKEN_BITS__RD_BURST__SHIFT 0x6
#define SDMA0_CHICKEN_BITS__WR_BURST__SHIFT 0x8
#define SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa
#define SDMA0_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT 0xe
#define SDMA0_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT 0xf
#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10
#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11
#define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT 0x13
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT 0x14
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT 0x15
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT 0x16
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT 0x17
#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x18
#define SDMA0_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT 0x19
#define SDMA0_CHICKEN_BITS__RESERVED__SHIFT 0x1a
#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L
#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L
#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00000020L
#define SDMA0_CHICKEN_BITS__RD_BURST_MASK 0x000000C0L
#define SDMA0_CHICKEN_BITS__WR_BURST_MASK 0x00000300L
#define SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK 0x00003C00L
#define SDMA0_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK 0x00004000L
#define SDMA0_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK 0x00008000L
#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L
#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L
#define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK 0x00080000L
#define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK 0x00100000LAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.