drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_offset.h- Extension
.h- Size
- 1051825 bytes
- Lines
- 10003
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_11_5_0_OFFSET_HEADER
#define _gc_11_5_0_OFFSET_HEADER
// addressBlock: gc_sdma0_sdma0dec
// base address: 0x4980
#define regSDMA0_DEC_START 0x0000
#define regSDMA0_DEC_START_BASE_IDX 0
#define regSDMA0_F32_MISC_CNTL 0x000b
#define regSDMA0_F32_MISC_CNTL_BASE_IDX 0
#define regSDMA0_UCODE_VERSION 0x000d
#define regSDMA0_UCODE_VERSION_BASE_IDX 0
#define regSDMA0_GLOBAL_TIMESTAMP_LO 0x000f
#define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
#define regSDMA0_GLOBAL_TIMESTAMP_HI 0x0010
#define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
#define regSDMA0_POWER_CNTL 0x001a
#define regSDMA0_POWER_CNTL_BASE_IDX 0
#define regSDMA0_CNTL 0x001c
#define regSDMA0_CNTL_BASE_IDX 0
#define regSDMA0_CHICKEN_BITS 0x001d
#define regSDMA0_CHICKEN_BITS_BASE_IDX 0
#define regSDMA0_GB_ADDR_CONFIG 0x001e
#define regSDMA0_GB_ADDR_CONFIG_BASE_IDX 0
#define regSDMA0_GB_ADDR_CONFIG_READ 0x001f
#define regSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0
#define regSDMA0_RB_RPTR_FETCH 0x0020
#define regSDMA0_RB_RPTR_FETCH_BASE_IDX 0
#define regSDMA0_RB_RPTR_FETCH_HI 0x0021
#define regSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0
#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0022
#define regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0
#define regSDMA0_IB_OFFSET_FETCH 0x0023
#define regSDMA0_IB_OFFSET_FETCH_BASE_IDX 0
#define regSDMA0_PROGRAM 0x0024
#define regSDMA0_PROGRAM_BASE_IDX 0
#define regSDMA0_STATUS_REG 0x0025
#define regSDMA0_STATUS_REG_BASE_IDX 0
#define regSDMA0_STATUS1_REG 0x0026
#define regSDMA0_STATUS1_REG_BASE_IDX 0
#define regSDMA0_CNTL1 0x0027
#define regSDMA0_CNTL1_BASE_IDX 0
#define regSDMA0_HBM_PAGE_CONFIG 0x0028
#define regSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0
#define regSDMA0_UCODE_CHECKSUM 0x0029
#define regSDMA0_UCODE_CHECKSUM_BASE_IDX 0
#define regSDMA0_FREEZE 0x002b
#define regSDMA0_FREEZE_BASE_IDX 0
#define regSDMA0_PROCESS_QUANTUM0 0x002c
#define regSDMA0_PROCESS_QUANTUM0_BASE_IDX 0
#define regSDMA0_PROCESS_QUANTUM1 0x002d
#define regSDMA0_PROCESS_QUANTUM1_BASE_IDX 0
#define regSDMA0_WATCHDOG_CNTL 0x002e
#define regSDMA0_WATCHDOG_CNTL_BASE_IDX 0
#define regSDMA0_QUEUE_STATUS0 0x002f
#define regSDMA0_QUEUE_STATUS0_BASE_IDX 0
#define regSDMA0_EDC_CONFIG 0x0032
#define regSDMA0_EDC_CONFIG_BASE_IDX 0
#define regSDMA0_BA_THRESHOLD 0x0033
#define regSDMA0_BA_THRESHOLD_BASE_IDX 0
#define regSDMA0_ID 0x0034
#define regSDMA0_ID_BASE_IDX 0
#define regSDMA0_VERSION 0x0035
#define regSDMA0_VERSION_BASE_IDX 0
#define regSDMA0_EDC_COUNTER 0x0036
#define regSDMA0_EDC_COUNTER_BASE_IDX 0
#define regSDMA0_EDC_COUNTER_CLEAR 0x0037
#define regSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0
#define regSDMA0_STATUS2_REG 0x0038
#define regSDMA0_STATUS2_REG_BASE_IDX 0
#define regSDMA0_ATOMIC_CNTL 0x0039
#define regSDMA0_ATOMIC_CNTL_BASE_IDX 0
#define regSDMA0_ATOMIC_PREOP_LO 0x003a
#define regSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0
#define regSDMA0_ATOMIC_PREOP_HI 0x003b
#define regSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0
#define regSDMA0_UTCL1_CNTL 0x003c
#define regSDMA0_UTCL1_CNTL_BASE_IDX 0
#define regSDMA0_UTCL1_WATERMK 0x003d
#define regSDMA0_UTCL1_WATERMK_BASE_IDX 0
#define regSDMA0_UTCL1_TIMEOUT 0x003e
#define regSDMA0_UTCL1_TIMEOUT_BASE_IDX 0
#define regSDMA0_UTCL1_PAGE 0x003f
#define regSDMA0_UTCL1_PAGE_BASE_IDX 0
#define regSDMA0_UTCL1_RD_STATUS 0x0040
#define regSDMA0_UTCL1_RD_STATUS_BASE_IDX 0
#define regSDMA0_UTCL1_WR_STATUS 0x0041
#define regSDMA0_UTCL1_WR_STATUS_BASE_IDX 0
#define regSDMA0_UTCL1_INV0 0x0042Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.