drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h- Extension
.h- Size
- 344221 bytes
- Lines
- 3867
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_9_0_DEFAULT_HEADER
#define _gc_9_0_DEFAULT_HEADER
// addressBlock: gc_grbmdec
#define mmGRBM_CNTL_DEFAULT 0x00000018
#define mmGRBM_SKEW_CNTL_DEFAULT 0x00000020
#define mmGRBM_STATUS2_DEFAULT 0x00000000
#define mmGRBM_PWR_CNTL_DEFAULT 0x00000000
#define mmGRBM_STATUS_DEFAULT 0x00000000
#define mmGRBM_STATUS_SE0_DEFAULT 0x00000000
#define mmGRBM_STATUS_SE1_DEFAULT 0x00000000
#define mmGRBM_SOFT_RESET_DEFAULT 0x00000000
#define mmGRBM_CGTT_CLK_CNTL_DEFAULT 0x00000100
#define mmGRBM_GFX_CLKEN_CNTL_DEFAULT 0x00001008
#define mmGRBM_WAIT_IDLE_CLOCKS_DEFAULT 0x00000030
#define mmGRBM_STATUS_SE2_DEFAULT 0x00000000
#define mmGRBM_STATUS_SE3_DEFAULT 0x00000000
#define mmGRBM_READ_ERROR_DEFAULT 0x00000000
#define mmGRBM_READ_ERROR2_DEFAULT 0x00000000
#define mmGRBM_INT_CNTL_DEFAULT 0x00000000
#define mmGRBM_TRAP_OP_DEFAULT 0x00000000
#define mmGRBM_TRAP_ADDR_DEFAULT 0x00000000
#define mmGRBM_TRAP_ADDR_MSK_DEFAULT 0x0003ffff
#define mmGRBM_TRAP_WD_DEFAULT 0x00000000
#define mmGRBM_TRAP_WD_MSK_DEFAULT 0xffffffff
#define mmGRBM_DSM_BYPASS_DEFAULT 0x00000000
#define mmGRBM_WRITE_ERROR_DEFAULT 0x00000000
#define mmGRBM_IOV_ERROR_DEFAULT 0x00000000
#define mmGRBM_CHIP_REVISION_DEFAULT 0x00000000
#define mmGRBM_GFX_CNTL_DEFAULT 0x00000000
#define mmGRBM_RSMU_CFG_DEFAULT 0x00011000
#define mmGRBM_IH_CREDIT_DEFAULT 0x00010000
#define mmGRBM_PWR_CNTL2_DEFAULT 0x00010000
#define mmGRBM_UTCL2_INVAL_RANGE_START_DEFAULT 0x00002891
#define mmGRBM_UTCL2_INVAL_RANGE_END_DEFAULT 0x000028ea
#define mmGRBM_RSMU_READ_ERROR_DEFAULT 0x00000000
#define mmGRBM_CHICKEN_BITS_DEFAULT 0x00000000
#define mmGRBM_NOWHERE_DEFAULT 0x00000000
#define mmGRBM_SCRATCH_REG0_DEFAULT 0x00000000
#define mmGRBM_SCRATCH_REG1_DEFAULT 0x00000000
#define mmGRBM_SCRATCH_REG2_DEFAULT 0x00000000
#define mmGRBM_SCRATCH_REG3_DEFAULT 0x00000000
#define mmGRBM_SCRATCH_REG4_DEFAULT 0x00000000
#define mmGRBM_SCRATCH_REG5_DEFAULT 0x00000000
#define mmGRBM_SCRATCH_REG6_DEFAULT 0x00000000
#define mmGRBM_SCRATCH_REG7_DEFAULT 0x00000000
// addressBlock: gc_cpdec
#define mmCP_CPC_STATUS_DEFAULT 0x00000000
#define mmCP_CPC_BUSY_STAT_DEFAULT 0x00000000
#define mmCP_CPC_STALLED_STAT1_DEFAULT 0x00000000
#define mmCP_CPF_STATUS_DEFAULT 0x00000000
#define mmCP_CPF_BUSY_STAT_DEFAULT 0x00000000
#define mmCP_CPF_STALLED_STAT1_DEFAULT 0x00000000
#define mmCP_CPC_GRBM_FREE_COUNT_DEFAULT 0x00000008
#define mmCP_MEC_CNTL_DEFAULT 0x50000000
#define mmCP_MEC_ME1_HEADER_DUMP_DEFAULT 0x00000000
#define mmCP_MEC_ME2_HEADER_DUMP_DEFAULT 0x00000000
#define mmCP_CPC_SCRATCH_INDEX_DEFAULT 0x00000000
#define mmCP_CPC_SCRATCH_DATA_DEFAULT 0x00000000
#define mmCP_CPF_GRBM_FREE_COUNT_DEFAULT 0x00000004
#define mmCP_CPC_HALT_HYST_COUNT_DEFAULT 0x00000002
#define mmCP_PRT_LOD_STATS_CNTL0_DEFAULT 0x00000000
#define mmCP_PRT_LOD_STATS_CNTL1_DEFAULT 0x00000000
#define mmCP_PRT_LOD_STATS_CNTL2_DEFAULT 0x00000000
#define mmCP_PRT_LOD_STATS_CNTL3_DEFAULT 0x00000000
#define mmCP_CE_COMPARE_COUNT_DEFAULT 0x00000000
#define mmCP_CE_DE_COUNT_DEFAULT 0x00000000
#define mmCP_DE_CE_COUNT_DEFAULT 0x00000000
#define mmCP_DE_LAST_INVAL_COUNT_DEFAULT 0x00000000
#define mmCP_DE_DE_COUNT_DEFAULT 0x00000000
#define mmCP_STALLED_STAT3_DEFAULT 0x00000000
#define mmCP_STALLED_STAT1_DEFAULT 0x00000000
#define mmCP_STALLED_STAT2_DEFAULT 0x00000000
#define mmCP_BUSY_STAT_DEFAULT 0x00000000
#define mmCP_STAT_DEFAULT 0x00000000
#define mmCP_ME_HEADER_DUMP_DEFAULT 0x00000000
#define mmCP_PFP_HEADER_DUMP_DEFAULT 0x00000000
#define mmCP_GRBM_FREE_COUNT_DEFAULT 0x00080808
#define mmCP_CE_HEADER_DUMP_DEFAULT 0x00000000
#define mmCP_PFP_INSTR_PNTR_DEFAULT 0x00000000
#define mmCP_ME_INSTR_PNTR_DEFAULT 0x00000000
#define mmCP_CE_INSTR_PNTR_DEFAULT 0x00000000
#define mmCP_MEC1_INSTR_PNTR_DEFAULT 0x00000000
#define mmCP_MEC2_INSTR_PNTR_DEFAULT 0x00000000
#define mmCP_CSF_STAT_DEFAULT 0x00000000
#define mmCP_ME_CNTL_DEFAULT 0x15000000
#define mmCP_CNTX_STAT_DEFAULT 0x00000000Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.