drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h- Extension
.h- Size
- 3303247 bytes
- Lines
- 31177
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_9_1_SH_MASK_HEADER
#define _gc_9_1_SH_MASK_HEADER
// addressBlock: gc_grbmdec
//GRBM_CNTL
#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
//GRBM_SKEW_CNTL
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
//GRBM_STATUS2
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L
#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L
#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L
//GRBM_PWR_CNTL
#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
//GRBM_STATUS
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.