drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h- Extension
.h- Size
- 80942 bytes
- Lines
- 765
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_9_4_1_SH_MASK_HEADER
#define _gc_9_4_1_SH_MASK_HEADER
// addressBlock: gc_cppdec2
//CPF_EDC_TAG_CNT
#define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0
#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2
#define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L
#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL
//CPF_EDC_ROQ_CNT
#define CPF_EDC_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0
#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2
#define CPF_EDC_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4
#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6
#define CPF_EDC_ROQ_CNT__DED_COUNT_ME1_MASK 0x00000003L
#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME1_MASK 0x0000000CL
#define CPF_EDC_ROQ_CNT__DED_COUNT_ME2_MASK 0x00000030L
#define CPF_EDC_ROQ_CNT__SEC_COUNT_ME2_MASK 0x000000C0L
//CPG_EDC_TAG_CNT
#define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0
#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2
#define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L
#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL
//CPG_EDC_DMA_CNT
#define CPG_EDC_DMA_CNT__ROQ_DED_COUNT__SHIFT 0x0
#define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT__SHIFT 0x2
#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x4
#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x6
#define CPG_EDC_DMA_CNT__ROQ_DED_COUNT_MASK 0x00000003L
#define CPG_EDC_DMA_CNT__ROQ_SEC_COUNT_MASK 0x0000000CL
#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x00000030L
#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x000000C0L
//CPC_EDC_SCRATCH_CNT
#define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0
#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2
#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L
#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL
//CPC_EDC_UCODE_CNT
#define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0
#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2
#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L
#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL
//DC_EDC_STATE_CNT
#define DC_EDC_STATE_CNT__DED_COUNT_ME1__SHIFT 0x0
#define DC_EDC_STATE_CNT__SEC_COUNT_ME1__SHIFT 0x2
#define DC_EDC_STATE_CNT__DED_COUNT_ME1_MASK 0x00000003L
#define DC_EDC_STATE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL
//DC_EDC_CSINVOC_CNT
#define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1__SHIFT 0x0
#define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1__SHIFT 0x2
#define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1__SHIFT 0x4
#define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1__SHIFT 0x6
#define DC_EDC_CSINVOC_CNT__DED_COUNT_ME1_MASK 0x00000003L
#define DC_EDC_CSINVOC_CNT__SEC_COUNT_ME1_MASK 0x0000000CL
#define DC_EDC_CSINVOC_CNT__DED_COUNT1_ME1_MASK 0x00000030L
#define DC_EDC_CSINVOC_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L
//DC_EDC_RESTORE_CNT
#define DC_EDC_RESTORE_CNT__DED_COUNT_ME1__SHIFT 0x0
#define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1__SHIFT 0x2
#define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1__SHIFT 0x4
#define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1__SHIFT 0x6
#define DC_EDC_RESTORE_CNT__DED_COUNT_ME1_MASK 0x00000003L
#define DC_EDC_RESTORE_CNT__SEC_COUNT_ME1_MASK 0x0000000CL
#define DC_EDC_RESTORE_CNT__DED_COUNT1_ME1_MASK 0x00000030L
#define DC_EDC_RESTORE_CNT__SEC_COUNT1_ME1_MASK 0x000000C0L
// addressBlock: gc_gdsdec
//GDS_EDC_CNT
#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0
#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4
#define GDS_EDC_CNT__UNUSED__SHIFT 0x6
#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L
#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L
#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L
//GDS_EDC_GRBM_CNT
#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2
#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4
#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L
#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL
#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L
//GDS_EDC_OA_DED
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3
#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.