drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_offset.h- Extension
.h- Size
- 815581 bytes
- Lines
- 7688
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_9_4_2_OFFSET_HEADER
#define _gc_9_4_2_OFFSET_HEADER
// addressBlock: didtind
// base address: 0x0
#define ixDIDT_SQ_CTRL0 0x0000
#define ixDIDT_SQ_CTRL2 0x0002
#define ixDIDT_SQ_STALL_CTRL 0x0004
#define ixDIDT_SQ_TUNING_CTRL 0x0005
#define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
#define ixDIDT_SQ_CTRL3 0x0007
#define ixDIDT_SQ_STALL_PATTERN_1_2 0x0008
#define ixDIDT_SQ_STALL_PATTERN_3_4 0x0009
#define ixDIDT_SQ_STALL_PATTERN_5_6 0x000a
#define ixDIDT_SQ_STALL_PATTERN_7 0x000b
#define ixDIDT_SQ_MPD_SCALE_FACTOR 0x000c
#define ixDIDT_SQ_THROTTLE_CNTL0 0x000d
#define ixDIDT_SQ_THROTTLE_CNTL1 0x000e
#define ixDIDT_SQ_THROTTLE_CNTL_STATUS 0x000f
#define ixDIDT_SQ_WEIGHT0_3 0x0010
#define ixDIDT_SQ_WEIGHT4_7 0x0011
#define ixDIDT_SQ_WEIGHT8_11 0x0012
#define ixDIDT_SQ_EDC_CTRL 0x0013
#define ixDIDT_SQ_THROTTLE_CTRL 0x0014
#define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015
#define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016
#define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017
#define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018
#define ixDIDT_SQ_EDC_STATUS 0x0019
#define ixDIDT_SQ_EDC_STALL_DELAY_1 0x001a
#define ixDIDT_SQ_EDC_STALL_DELAY_2 0x001b
#define ixDIDT_SQ_EDC_STALL_DELAY_3 0x001c
#define ixDIDT_SQ_EDC_STALL_DELAY_4 0x001d
#define ixDIDT_SQ_EDC_OVERFLOW 0x001e
#define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA 0x001f
#define ixDIDT_DB_CTRL0 0x0020
#define ixDIDT_DB_CTRL2 0x0022
#define ixDIDT_DB_STALL_CTRL 0x0024
#define ixDIDT_DB_TUNING_CTRL 0x0025
#define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL 0x0026
#define ixDIDT_DB_CTRL3 0x0027
#define ixDIDT_DB_STALL_PATTERN_1_2 0x0028
#define ixDIDT_DB_STALL_PATTERN_3_4 0x0029
#define ixDIDT_DB_STALL_PATTERN_5_6 0x002a
#define ixDIDT_DB_STALL_PATTERN_7 0x002b
#define ixDIDT_DB_MPD_SCALE_FACTOR 0x002c
#define ixDIDT_DB_THROTTLE_CNTL0 0x002d
#define ixDIDT_DB_THROTTLE_CNTL1 0x002e
#define ixDIDT_DB_THROTTLE_CNTL_STATUS 0x002f
#define ixDIDT_DB_WEIGHT0_3 0x0030
#define ixDIDT_DB_WEIGHT4_7 0x0031
#define ixDIDT_DB_WEIGHT8_11 0x0032
#define ixDIDT_DB_EDC_CTRL 0x0033
#define ixDIDT_DB_THROTTLE_CTRL 0x0034
#define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035
#define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036
#define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037
#define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038
#define ixDIDT_DB_EDC_STATUS 0x0039
#define ixDIDT_DB_EDC_STALL_DELAY_1 0x003a
#define ixDIDT_DB_EDC_OVERFLOW 0x003e
#define ixDIDT_DB_EDC_ROLLING_POWER_DELTA 0x003f
#define ixDIDT_TD_CTRL0 0x0040
#define ixDIDT_TD_CTRL2 0x0042
#define ixDIDT_TD_STALL_CTRL 0x0044
#define ixDIDT_TD_TUNING_CTRL 0x0045
#define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL 0x0046
#define ixDIDT_TD_CTRL3 0x0047
#define ixDIDT_TD_STALL_PATTERN_1_2 0x0048
#define ixDIDT_TD_STALL_PATTERN_3_4 0x0049
#define ixDIDT_TD_STALL_PATTERN_5_6 0x004a
#define ixDIDT_TD_STALL_PATTERN_7 0x004b
#define ixDIDT_TD_MPD_SCALE_FACTOR 0x004c
#define ixDIDT_TD_THROTTLE_CNTL0 0x004d
#define ixDIDT_TD_THROTTLE_CNTL1 0x004e
#define ixDIDT_TD_THROTTLE_CNTL_STATUS 0x004f
#define ixDIDT_TD_WEIGHT0_3 0x0050
#define ixDIDT_TD_WEIGHT4_7 0x0051
#define ixDIDT_TD_WEIGHT8_11 0x0052
#define ixDIDT_TD_EDC_CTRL 0x0053
#define ixDIDT_TD_THROTTLE_CTRL 0x0054
#define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055
#define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056
#define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057
#define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058
#define ixDIDT_TD_EDC_STATUS 0x0059
#define ixDIDT_TD_EDC_STALL_DELAY_1 0x005a
#define ixDIDT_TD_EDC_STALL_DELAY_2 0x005bAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.