drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h- Extension
.h- Size
- 3509832 bytes
- Lines
- 33004
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_9_4_2_SH_MASK_HEADER
#define _gc_9_4_2_SH_MASK_HEADER
// addressBlock: didtind
//DIDT_SQ_CTRL0
#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1
#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3
#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4
#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5
#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6
#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7
#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8
#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a
#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN__SHIFT 0x1b
#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL__SHIFT 0x1c
#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L
#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L
#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L
#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L
#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L
#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L
#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L
#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L
#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L
#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L
#define DIDT_SQ_CTRL0__DIDT_RLC_FORCE_STALL_EN_MASK 0x08000000L
#define DIDT_SQ_CTRL0__DIDT_RLC_STALL_LEVEL_SEL_MASK 0x10000000L
//DIDT_SQ_CTRL2
#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL
#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L
#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L
//DIDT_SQ_STALL_CTRL
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L
#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L
//DIDT_SQ_TUNING_CTRL
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L
//DIDT_SQ_STALL_AUTO_RELEASE_CTRL
#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0
#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL
//DIDT_SQ_CTRL3
#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0
#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1
#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2
#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4
#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9
#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe
#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16
#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17
#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18
#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b
#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c
#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L
#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L
#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL
#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L
#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L
#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L
#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L
#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L
#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L
#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L
#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L
#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L
//DIDT_SQ_STALL_PATTERN_1_2
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL
#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L
//DIDT_SQ_STALL_PATTERN_3_4
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10
#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFLAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.