drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_offset.h- Extension
.h- Size
- 790032 bytes
- Lines
- 7451
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _gc_9_4_3_OFFSET_HEADER
#define _gc_9_4_3_OFFSET_HEADER
// addressBlock: xcd0_gc_grbmdec
// base address: 0x8000
#define regGRBM_CNTL 0x0000
#define regGRBM_CNTL_BASE_IDX 0
#define regGRBM_SKEW_CNTL 0x0001
#define regGRBM_SKEW_CNTL_BASE_IDX 0
#define regGRBM_STATUS2 0x0002
#define regGRBM_STATUS2_BASE_IDX 0
#define regGRBM_PWR_CNTL 0x0003
#define regGRBM_PWR_CNTL_BASE_IDX 0
#define regGRBM_STATUS 0x0004
#define regGRBM_STATUS_BASE_IDX 0
#define regGRBM_STATUS_SE0 0x0005
#define regGRBM_STATUS_SE0_BASE_IDX 0
#define regGRBM_STATUS_SE1 0x0006
#define regGRBM_STATUS_SE1_BASE_IDX 0
#define regGRBM_SOFT_RESET 0x0008
#define regGRBM_SOFT_RESET_BASE_IDX 0
#define regGRBM_GFX_CLKEN_CNTL 0x000c
#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0
#define regGRBM_WAIT_IDLE_CLOCKS 0x000d
#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0
#define regGRBM_STATUS_SE2 0x000e
#define regGRBM_STATUS_SE2_BASE_IDX 0
#define regGRBM_STATUS_SE3 0x000f
#define regGRBM_STATUS_SE3_BASE_IDX 0
#define regGRBM_READ_ERROR 0x0016
#define regGRBM_READ_ERROR_BASE_IDX 0
#define regGRBM_READ_ERROR2 0x0017
#define regGRBM_READ_ERROR2_BASE_IDX 0
#define regGRBM_INT_CNTL 0x0018
#define regGRBM_INT_CNTL_BASE_IDX 0
#define regGRBM_TRAP_OP 0x0019
#define regGRBM_TRAP_OP_BASE_IDX 0
#define regGRBM_TRAP_ADDR 0x001a
#define regGRBM_TRAP_ADDR_BASE_IDX 0
#define regGRBM_TRAP_ADDR_MSK 0x001b
#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0
#define regGRBM_TRAP_WD 0x001c
#define regGRBM_TRAP_WD_BASE_IDX 0
#define regGRBM_TRAP_WD_MSK 0x001d
#define regGRBM_TRAP_WD_MSK_BASE_IDX 0
#define regGRBM_WRITE_ERROR 0x001f
#define regGRBM_WRITE_ERROR_BASE_IDX 0
#define regGRBM_IOV_ERROR 0x0020
#define regGRBM_IOV_ERROR_BASE_IDX 0
#define regGRBM_CHIP_REVISION 0x0021
#define regGRBM_CHIP_REVISION_BASE_IDX 0
#define regGRBM_GFX_CNTL 0x0022
#define regGRBM_GFX_CNTL_BASE_IDX 0
#define regGRBM_RSMU_CFG 0x0023
#define regGRBM_RSMU_CFG_BASE_IDX 0
#define regGRBM_IH_CREDIT 0x0024
#define regGRBM_IH_CREDIT_BASE_IDX 0
#define regGRBM_PWR_CNTL2 0x0025
#define regGRBM_PWR_CNTL2_BASE_IDX 0
#define regGRBM_UTCL2_INVAL_RANGE_START 0x0026
#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0
#define regGRBM_UTCL2_INVAL_RANGE_END 0x0027
#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0
#define regGRBM_RSMU_READ_ERROR 0x0028
#define regGRBM_RSMU_READ_ERROR_BASE_IDX 0
#define regGRBM_CHICKEN_BITS 0x0029
#define regGRBM_CHICKEN_BITS_BASE_IDX 0
#define regGRBM_FENCE_RANGE0 0x002a
#define regGRBM_FENCE_RANGE0_BASE_IDX 0
#define regGRBM_FENCE_RANGE1 0x002b
#define regGRBM_FENCE_RANGE1_BASE_IDX 0
#define regGRBM_IOV_READ_ERROR 0x002c
#define regGRBM_IOV_READ_ERROR_BASE_IDX 0
#define regGRBM_NOWHERE 0x003f
#define regGRBM_NOWHERE_BASE_IDX 0
#define regGRBM_SCRATCH_REG0 0x0040
#define regGRBM_SCRATCH_REG0_BASE_IDX 0
#define regGRBM_SCRATCH_REG1 0x0041
#define regGRBM_SCRATCH_REG1_BASE_IDX 0
#define regGRBM_SCRATCH_REG2 0x0042
#define regGRBM_SCRATCH_REG2_BASE_IDX 0
#define regGRBM_SCRATCH_REG3 0x0043
#define regGRBM_SCRATCH_REG3_BASE_IDX 0
#define regGRBM_SCRATCH_REG4 0x0044
#define regGRBM_SCRATCH_REG4_BASE_IDX 0
#define regGRBM_SCRATCH_REG5 0x0045
#define regGRBM_SCRATCH_REG5_BASE_IDX 0
#define regGRBM_SCRATCH_REG6 0x0046Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.