drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_d.h- Extension
.h- Size
- 66039 bytes
- Lines
- 1787
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef GFX_6_0_D_H
#define GFX_6_0_D_H
#define ixCLIPPER_DEBUG_REG00 0x0000
#define ixCLIPPER_DEBUG_REG01 0x0001
#define ixCLIPPER_DEBUG_REG02 0x0002
#define ixCLIPPER_DEBUG_REG03 0x0003
#define ixCLIPPER_DEBUG_REG04 0x0004
#define ixCLIPPER_DEBUG_REG05 0x0005
#define ixCLIPPER_DEBUG_REG06 0x0006
#define ixCLIPPER_DEBUG_REG07 0x0007
#define ixCLIPPER_DEBUG_REG08 0x0008
#define ixCLIPPER_DEBUG_REG09 0x0009
#define ixCLIPPER_DEBUG_REG10 0x000A
#define ixCLIPPER_DEBUG_REG11 0x000B
#define ixCLIPPER_DEBUG_REG12 0x000C
#define ixCLIPPER_DEBUG_REG13 0x000D
#define ixCLIPPER_DEBUG_REG14 0x000E
#define ixCLIPPER_DEBUG_REG15 0x000F
#define ixCLIPPER_DEBUG_REG16 0x0010
#define ixCLIPPER_DEBUG_REG17 0x0011
#define ixCLIPPER_DEBUG_REG18 0x0012
#define ixCLIPPER_DEBUG_REG19 0x0013
#define ixGDS_DEBUG_REG0 0x0000
#define ixGDS_DEBUG_REG1 0x0001
#define ixGDS_DEBUG_REG2 0x0002
#define ixGDS_DEBUG_REG3 0x0003
#define ixGDS_DEBUG_REG4 0x0004
#define ixGDS_DEBUG_REG5 0x0005
#define ixGDS_DEBUG_REG6 0x0006
#define ixIA_DEBUG_REG0 0x0000
#define ixIA_DEBUG_REG1 0x0001
#define ixIA_DEBUG_REG2 0x0002
#define ixIA_DEBUG_REG3 0x0003
#define ixIA_DEBUG_REG4 0x0004
#define ixIA_DEBUG_REG5 0x0005
#define ixIA_DEBUG_REG6 0x0006
#define ixIA_DEBUG_REG7 0x0007
#define ixIA_DEBUG_REG8 0x0008
#define ixIA_DEBUG_REG9 0x0009
#define ixPA_SC_DEBUG_REG0 0x0000
#define ixPA_SC_DEBUG_REG1 0x0001
#define ixSETUP_DEBUG_REG0 0x0018
#define ixSETUP_DEBUG_REG1 0x0019
#define ixSETUP_DEBUG_REG2 0x001A
#define ixSETUP_DEBUG_REG3 0x001B
#define ixSETUP_DEBUG_REG4 0x001C
#define ixSETUP_DEBUG_REG5 0x001D
#define ixSQ_DEBUG_CTRL_LOCAL 0x0009
#define ixSQ_DEBUG_STS_LOCAL 0x0008
#define ixSQ_INTERRUPT_WORD_AUTO 0x20C0
#define ixSQ_INTERRUPT_WORD_CMN 0x20C0
#define ixSQ_INTERRUPT_WORD_WAVE 0x20C0
#define ixSQ_WAVE_EXEC_HI 0x027F
#define ixSQ_WAVE_EXEC_LO 0x027E
#define ixSQ_WAVE_GPR_ALLOC 0x0015
#define ixSQ_WAVE_HW_ID 0x0014
#define ixSQ_WAVE_IB_DBG0 0x001C
#define ixSQ_WAVE_IB_STS 0x0017
#define ixSQ_WAVE_INST_DW0 0x001A
#define ixSQ_WAVE_INST_DW1 0x001B
#define ixSQ_WAVE_LDS_ALLOC 0x0016
#define ixSQ_WAVE_M0 0x027C
#define ixSQ_WAVE_MODE 0x0011
#define ixSQ_WAVE_PC_HI 0x0019
#define ixSQ_WAVE_PC_LO 0x0018
#define ixSQ_WAVE_STATUS 0x0012
#define ixSQ_WAVE_TBA_HI 0x026D
#define ixSQ_WAVE_TBA_LO 0x026C
#define ixSQ_WAVE_TMA_HI 0x026F
#define ixSQ_WAVE_TMA_LO 0x026E
#define ixSQ_WAVE_TRAPSTS 0x0013
#define ixSQ_WAVE_TTMP0 0x0270
#define ixSQ_WAVE_TTMP10 0x027A
#define ixSQ_WAVE_TTMP1 0x0271
#define ixSQ_WAVE_TTMP11 0x027B
#define ixSQ_WAVE_TTMP2 0x0272
#define ixSQ_WAVE_TTMP3 0x0273
#define ixSQ_WAVE_TTMP4 0x0274
#define ixSQ_WAVE_TTMP5 0x0275
#define ixSQ_WAVE_TTMP6 0x0276
#define ixSQ_WAVE_TTMP7 0x0277
#define ixSQ_WAVE_TTMP8 0x0278
#define ixSQ_WAVE_TTMP9 0x0279
#define ixSXIFCCG_DEBUG_REG0 0x0014
#define ixSXIFCCG_DEBUG_REG1 0x0015
#define ixSXIFCCG_DEBUG_REG2 0x0016
#define ixSXIFCCG_DEBUG_REG3 0x0017
#define ixVGT_DEBUG_REG0 0x0000
#define ixVGT_DEBUG_REG10 0x000A
Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.