drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

Extension

.h

Size

1006272 bytes

Lines

18445

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef GFX_7_2_SH_MASK_H
#define GFX_7_2_SH_MASK_H

#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
#define CB_COLOR_CONTROL__MODE_MASK 0x70
#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.