drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_7_1_sh_mask.h

Extension

.h

Size

751012 bytes

Lines

14417

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef GMC_7_1_SH_MASK_H
#define GMC_7_1_SH_MASK_H

#define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
#define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
#define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
#define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
#define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
#define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
#define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
#define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
#define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
#define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
#define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
#define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
#define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
#define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
#define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
#define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
#define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
#define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
#define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
#define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
#define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
#define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
#define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
#define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
#define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
#define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
#define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
#define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
#define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
#define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
#define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
#define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
#define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
#define MC_ARB_FED_CNTL__MODE_MASK 0x3
#define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
#define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
#define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
#define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
#define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
#define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.