drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/gmc/gmc_8_2_enum.h- Extension
.h- Size
- 56776 bytes
- Lines
- 1069
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef GMC_8_2_ENUM_H
#define GMC_8_2_ENUM_H
typedef enum DebugBlockId {
DBG_BLOCK_ID_RESERVED = 0x0,
DBG_BLOCK_ID_DBG = 0x1,
DBG_BLOCK_ID_VMC = 0x2,
DBG_BLOCK_ID_PDMA = 0x3,
DBG_BLOCK_ID_CG = 0x4,
DBG_BLOCK_ID_SRBM = 0x5,
DBG_BLOCK_ID_GRBM = 0x6,
DBG_BLOCK_ID_RLC = 0x7,
DBG_BLOCK_ID_CSC = 0x8,
DBG_BLOCK_ID_SEM = 0x9,
DBG_BLOCK_ID_IH = 0xa,
DBG_BLOCK_ID_SC = 0xb,
DBG_BLOCK_ID_SQ = 0xc,
DBG_BLOCK_ID_UVDU = 0xd,
DBG_BLOCK_ID_SQA = 0xe,
DBG_BLOCK_ID_SDMA0 = 0xf,
DBG_BLOCK_ID_SDMA1 = 0x10,
DBG_BLOCK_ID_SPIM = 0x11,
DBG_BLOCK_ID_GDS = 0x12,
DBG_BLOCK_ID_VC0 = 0x13,
DBG_BLOCK_ID_VC1 = 0x14,
DBG_BLOCK_ID_PA0 = 0x15,
DBG_BLOCK_ID_PA1 = 0x16,
DBG_BLOCK_ID_CP0 = 0x17,
DBG_BLOCK_ID_CP1 = 0x18,
DBG_BLOCK_ID_CP2 = 0x19,
DBG_BLOCK_ID_XBR = 0x1a,
DBG_BLOCK_ID_UVDM = 0x1b,
DBG_BLOCK_ID_VGT0 = 0x1c,
DBG_BLOCK_ID_VGT1 = 0x1d,
DBG_BLOCK_ID_IA = 0x1e,
DBG_BLOCK_ID_SXM0 = 0x1f,
DBG_BLOCK_ID_SXM1 = 0x20,
DBG_BLOCK_ID_SCT0 = 0x21,
DBG_BLOCK_ID_SCT1 = 0x22,
DBG_BLOCK_ID_SPM0 = 0x23,
DBG_BLOCK_ID_SPM1 = 0x24,
DBG_BLOCK_ID_UNUSED0 = 0x25,
DBG_BLOCK_ID_UNUSED1 = 0x26,
DBG_BLOCK_ID_TCAA = 0x27,
DBG_BLOCK_ID_TCAB = 0x28,
DBG_BLOCK_ID_TCCA = 0x29,
DBG_BLOCK_ID_TCCB = 0x2a,
DBG_BLOCK_ID_MCC0 = 0x2b,
DBG_BLOCK_ID_MCC1 = 0x2c,
DBG_BLOCK_ID_MCC2 = 0x2d,
DBG_BLOCK_ID_MCC3 = 0x2e,
DBG_BLOCK_ID_SXS0 = 0x2f,
DBG_BLOCK_ID_SXS1 = 0x30,
DBG_BLOCK_ID_SXS2 = 0x31,
DBG_BLOCK_ID_SXS3 = 0x32,
DBG_BLOCK_ID_SXS4 = 0x33,
DBG_BLOCK_ID_SXS5 = 0x34,
DBG_BLOCK_ID_SXS6 = 0x35,
DBG_BLOCK_ID_SXS7 = 0x36,
DBG_BLOCK_ID_SXS8 = 0x37,
DBG_BLOCK_ID_SXS9 = 0x38,
DBG_BLOCK_ID_BCI0 = 0x39,
DBG_BLOCK_ID_BCI1 = 0x3a,
DBG_BLOCK_ID_BCI2 = 0x3b,
DBG_BLOCK_ID_BCI3 = 0x3c,
DBG_BLOCK_ID_MCB = 0x3d,
DBG_BLOCK_ID_UNUSED6 = 0x3e,
DBG_BLOCK_ID_SQA00 = 0x3f,
DBG_BLOCK_ID_SQA01 = 0x40,
DBG_BLOCK_ID_SQA02 = 0x41,
DBG_BLOCK_ID_SQA10 = 0x42,
DBG_BLOCK_ID_SQA11 = 0x43,
DBG_BLOCK_ID_SQA12 = 0x44,
DBG_BLOCK_ID_UNUSED7 = 0x45,
DBG_BLOCK_ID_UNUSED8 = 0x46,
DBG_BLOCK_ID_SQB00 = 0x47,
DBG_BLOCK_ID_SQB01 = 0x48,
DBG_BLOCK_ID_SQB10 = 0x49,
DBG_BLOCK_ID_SQB11 = 0x4a,
DBG_BLOCK_ID_SQ00 = 0x4b,
DBG_BLOCK_ID_SQ01 = 0x4c,
DBG_BLOCK_ID_SQ10 = 0x4d,
DBG_BLOCK_ID_SQ11 = 0x4e,
DBG_BLOCK_ID_CB00 = 0x4f,
DBG_BLOCK_ID_CB01 = 0x50,
DBG_BLOCK_ID_CB02 = 0x51,
DBG_BLOCK_ID_CB03 = 0x52,
DBG_BLOCK_ID_CB04 = 0x53,
DBG_BLOCK_ID_UNUSED9 = 0x54,
DBG_BLOCK_ID_UNUSED10 = 0x55,Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.