drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
Extension
.h
Size
30754 bytes
Lines
604
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _hdp_4_0_SH_MASK_HEADER
#define _hdp_4_0_SH_MASK_HEADER


// addressBlock: hdp_hdpdec
//HDP_MMHUB_TLVL
#define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT	0x0
#define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT	0x4
#define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT	0x8
#define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT	0xc
#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT	0x10
#define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK	0x00000007L
#define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK	0x00000070L
#define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK	0x00000700L
#define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK	0x00007000L
#define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK	0x00070000L
//HDP_MMHUB_UNITID
#define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT	0x0
#define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT	0x8
#define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT	0x10
#define HDP_MMHUB_UNITID__HDP_UNITID_MASK	0x0000003FL
#define HDP_MMHUB_UNITID__XDP_UNITID_MASK	0x00003F00L
#define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK	0x003F0000L
//HDP_NONSURFACE_BASE
#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT	0x0
#define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK	0xFFFFFFFFL
//HDP_NONSURFACE_INFO
#define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT	0x4
#define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT	0x8
#define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK	0x00000030L
#define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK	0x00000F00L
//HDP_NONSURFACE_BASE_HI
#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT	0x0
#define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK	0x000000FFL
//HDP_NONSURF_FLAGS
#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT	0x0
#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT	0x1
#define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK	0x00000001L
#define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK	0x00000002L
//HDP_NONSURF_FLAGS_CLR
#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT	0x0
#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT	0x1
#define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK	0x00000001L
#define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK	0x00000002L
//HDP_HOST_PATH_CNTL
#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT	0x9
#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT	0xb
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT	0x12
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT	0x13
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT	0x15
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT	0x16
#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT	0x1d
#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT	0x1e
#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT	0x1f
#define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK	0x00000600L
#define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK	0x00001800L
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK	0x00040000L
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK	0x00180000L
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK	0x00200000L
#define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK	0x00400000L
#define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK	0x20000000L
#define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK	0x40000000L
#define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK	0x80000000L
//HDP_SW_SEMAPHORE
#define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT	0x0
#define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK	0xFFFFFFFFL
//HDP_DEBUG0
#define HDP_DEBUG0__HDP_DEBUG__SHIFT	0x0
#define HDP_DEBUG0__HDP_DEBUG_MASK	0xFFFFFFFFL
//HDP_LAST_SURFACE_HIT
#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT	0x0
#define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK	0x00000003L
//HDP_READ_CACHE_INVALIDATE
#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT	0x0
#define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK	0x00000001L
//HDP_OUTSTANDING_REQ
#define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT	0x0
#define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT	0x8
#define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK	0x000000FFL
#define HDP_OUTSTANDING_REQ__READ_REQ_MASK	0x0000FF00L
//HDP_MISC_CNTL
#define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT	0x0
#define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT	0x2
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT	0x5
#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT	0x6
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT	0xb
#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe
#define HDP_MISC_CNTL__FED_ENABLE__SHIFT	0x15
#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT	0x17
#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT	0x18

Annotation

Implementation Notes