drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_5_0_0_offset.h- Extension
.h- Size
- 21462 bytes
- Lines
- 218
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _hdp_5_0_0_OFFSET_HEADER
#define _hdp_5_0_0_OFFSET_HEADER
// addressBlock: hdp_hdpdec
// base address: 0x3c80
#define mmHDP_MMHUB_TLVL 0x0000
#define mmHDP_MMHUB_TLVL_BASE_IDX 0
#define mmHDP_MMHUB_UNITID 0x0001
#define mmHDP_MMHUB_UNITID_BASE_IDX 0
#define mmHDP_NONSURFACE_BASE 0x0040
#define mmHDP_NONSURFACE_BASE_BASE_IDX 0
#define mmHDP_NONSURFACE_INFO 0x0041
#define mmHDP_NONSURFACE_INFO_BASE_IDX 0
#define mmHDP_NONSURFACE_BASE_HI 0x0042
#define mmHDP_NONSURFACE_BASE_HI_BASE_IDX 0
#define mmHDP_SURFACE_WRITE_FLAGS 0x00c4
#define mmHDP_SURFACE_WRITE_FLAGS_BASE_IDX 0
#define mmHDP_SURFACE_READ_FLAGS 0x00c5
#define mmHDP_SURFACE_READ_FLAGS_BASE_IDX 0
#define mmHDP_SURFACE_WRITE_FLAGS_CLR 0x00c6
#define mmHDP_SURFACE_WRITE_FLAGS_CLR_BASE_IDX 0
#define mmHDP_SURFACE_READ_FLAGS_CLR 0x00c7
#define mmHDP_SURFACE_READ_FLAGS_CLR_BASE_IDX 0
#define mmHDP_NONSURF_FLAGS 0x00c8
#define mmHDP_NONSURF_FLAGS_BASE_IDX 0
#define mmHDP_NONSURF_FLAGS_CLR 0x00c9
#define mmHDP_NONSURF_FLAGS_CLR_BASE_IDX 0
#define mmHDP_HOST_PATH_CNTL 0x00cc
#define mmHDP_HOST_PATH_CNTL_BASE_IDX 0
#define mmHDP_SW_SEMAPHORE 0x00cd
#define mmHDP_SW_SEMAPHORE_BASE_IDX 0
#define mmHDP_LAST_SURFACE_HIT 0x00d0
#define mmHDP_LAST_SURFACE_HIT_BASE_IDX 0
#define mmHDP_READ_CACHE_INVALIDATE 0x00d1
#define mmHDP_READ_CACHE_INVALIDATE_BASE_IDX 0
#define mmHDP_OUTSTANDING_REQ 0x00d2
#define mmHDP_OUTSTANDING_REQ_BASE_IDX 0
#define mmHDP_MISC_CNTL 0x00d3
#define mmHDP_MISC_CNTL_BASE_IDX 0
#define mmHDP_MEM_POWER_CTRL 0x00d4
#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
#define mmHDP_MMHUB_CNTL 0x00d5
#define mmHDP_MMHUB_CNTL_BASE_IDX 0
#define mmHDP_EDC_CNT 0x00d6
#define mmHDP_EDC_CNT_BASE_IDX 0
#define mmHDP_VERSION 0x00d7
#define mmHDP_VERSION_BASE_IDX 0
#define mmHDP_CLK_CNTL 0x00d8
#define mmHDP_CLK_CNTL_BASE_IDX 0
#define mmHDP_MEMIO_CNTL 0x00f6
#define mmHDP_MEMIO_CNTL_BASE_IDX 0
#define mmHDP_MEMIO_ADDR 0x00f7
#define mmHDP_MEMIO_ADDR_BASE_IDX 0
#define mmHDP_MEMIO_STATUS 0x00f8
#define mmHDP_MEMIO_STATUS_BASE_IDX 0
#define mmHDP_MEMIO_WR_DATA 0x00f9
#define mmHDP_MEMIO_WR_DATA_BASE_IDX 0
#define mmHDP_MEMIO_RD_DATA 0x00fa
#define mmHDP_MEMIO_RD_DATA_BASE_IDX 0
#define mmHDP_XDP_DIRECT2HDP_FIRST 0x0100
#define mmHDP_XDP_DIRECT2HDP_FIRST_BASE_IDX 0
#define mmHDP_XDP_D2H_FLUSH 0x0101
#define mmHDP_XDP_D2H_FLUSH_BASE_IDX 0
#define mmHDP_XDP_D2H_BAR_UPDATE 0x0102
#define mmHDP_XDP_D2H_BAR_UPDATE_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_3 0x0103
#define mmHDP_XDP_D2H_RSVD_3_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_4 0x0104
#define mmHDP_XDP_D2H_RSVD_4_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_5 0x0105
#define mmHDP_XDP_D2H_RSVD_5_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_6 0x0106
#define mmHDP_XDP_D2H_RSVD_6_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_7 0x0107
#define mmHDP_XDP_D2H_RSVD_7_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_8 0x0108
#define mmHDP_XDP_D2H_RSVD_8_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_9 0x0109
#define mmHDP_XDP_D2H_RSVD_9_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_10 0x010a
#define mmHDP_XDP_D2H_RSVD_10_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_11 0x010b
#define mmHDP_XDP_D2H_RSVD_11_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_12 0x010c
#define mmHDP_XDP_D2H_RSVD_12_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_13 0x010d
#define mmHDP_XDP_D2H_RSVD_13_BASE_IDX 0
#define mmHDP_XDP_D2H_RSVD_14 0x010eAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.