drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_default.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_default.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_default.h- Extension
.h- Size
- 88241 bytes
- Lines
- 1012
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _mmhub_1_0_DEFAULT_HEADER
#define _mmhub_1_0_DEFAULT_HEADER
// addressBlock: mmhub_dagbdec
#define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9
#define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8
#define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x0000304f
#define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039
#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
#define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
#define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a10408
#define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7
#define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000
#define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000
#define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000
#define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000
#define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000
#define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000
#define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9
#define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8
#define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x0000304f
#define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039
#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888
#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111
#define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100
#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888
#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111
#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888
#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111
#define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001
#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111
#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000
#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111
#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000
#define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082
#define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.