drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_2_0_0_offset.h- Extension
.h- Size
- 186131 bytes
- Lines
- 1800
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _mmhub_2_0_0_OFFSET_HEADER
#define _mmhub_2_0_0_OFFSET_HEADER
// addressBlock: mmhub_dagbdec
// base address: 0x68000
#define mmDAGB0_RDCLI0 0x0000
#define mmDAGB0_RDCLI0_BASE_IDX 0
#define mmDAGB0_RDCLI1 0x0001
#define mmDAGB0_RDCLI1_BASE_IDX 0
#define mmDAGB0_RDCLI2 0x0002
#define mmDAGB0_RDCLI2_BASE_IDX 0
#define mmDAGB0_RDCLI3 0x0003
#define mmDAGB0_RDCLI3_BASE_IDX 0
#define mmDAGB0_RDCLI4 0x0004
#define mmDAGB0_RDCLI4_BASE_IDX 0
#define mmDAGB0_RDCLI5 0x0005
#define mmDAGB0_RDCLI5_BASE_IDX 0
#define mmDAGB0_RDCLI6 0x0006
#define mmDAGB0_RDCLI6_BASE_IDX 0
#define mmDAGB0_RDCLI7 0x0007
#define mmDAGB0_RDCLI7_BASE_IDX 0
#define mmDAGB0_RDCLI8 0x0008
#define mmDAGB0_RDCLI8_BASE_IDX 0
#define mmDAGB0_RDCLI9 0x0009
#define mmDAGB0_RDCLI9_BASE_IDX 0
#define mmDAGB0_RDCLI10 0x000a
#define mmDAGB0_RDCLI10_BASE_IDX 0
#define mmDAGB0_RDCLI11 0x000b
#define mmDAGB0_RDCLI11_BASE_IDX 0
#define mmDAGB0_RDCLI12 0x000c
#define mmDAGB0_RDCLI12_BASE_IDX 0
#define mmDAGB0_RDCLI13 0x000d
#define mmDAGB0_RDCLI13_BASE_IDX 0
#define mmDAGB0_RDCLI14 0x000e
#define mmDAGB0_RDCLI14_BASE_IDX 0
#define mmDAGB0_RDCLI15 0x000f
#define mmDAGB0_RDCLI15_BASE_IDX 0
#define mmDAGB0_RDCLI16 0x0010
#define mmDAGB0_RDCLI16_BASE_IDX 0
#define mmDAGB0_RDCLI17 0x0011
#define mmDAGB0_RDCLI17_BASE_IDX 0
#define mmDAGB0_RDCLI18 0x0012
#define mmDAGB0_RDCLI18_BASE_IDX 0
#define mmDAGB0_RD_CNTL 0x0013
#define mmDAGB0_RD_CNTL_BASE_IDX 0
#define mmDAGB0_RD_GMI_CNTL 0x0014
#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 0
#define mmDAGB0_RD_ADDR_DAGB 0x0015
#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 0
#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0016
#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0017
#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0018
#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0019
#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x001a
#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x001b
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x001c
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001d
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001e
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x001f
#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 0
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x0020
#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 0
#define mmDAGB0_RD_VC0_CNTL 0x0021
#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 0
#define mmDAGB0_RD_VC1_CNTL 0x0022
#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 0
#define mmDAGB0_RD_VC2_CNTL 0x0023
#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 0
#define mmDAGB0_RD_VC3_CNTL 0x0024
#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 0
#define mmDAGB0_RD_VC4_CNTL 0x0025
#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 0
#define mmDAGB0_RD_VC5_CNTL 0x0026
#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 0
#define mmDAGB0_RD_VC6_CNTL 0x0027
#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 0
#define mmDAGB0_RD_VC7_CNTL 0x0028
#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 0
#define mmDAGB0_RD_CNTL_MISC 0x0029Annotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.