drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_offset.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_offset.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_offset.h- Extension
.h- Size
- 79750 bytes
- Lines
- 803
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _mmhub_4_2_0_OFFSET_HEADER
#define _mmhub_4_2_0_OFFSET_HEADER
// addressBlock: mmhub_dagb_dagbdec
// base address: 0x60000
#define regDAGB0_CNTL_MISC2 0x00a7
#define regDAGB0_CNTL_MISC2_BASE_IDX 1
#define regDAGB1_CNTL_MISC2 0x01a7
#define regDAGB1_CNTL_MISC2_BASE_IDX 1
// addressBlock: mmhub_mm_cane_mmcanedec
// base address: 0x60c20
#define regMM_CANE_ICG_CTRL 0x0313
#define regMM_CANE_ICG_CTRL_BASE_IDX 1
// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
// base address: 0x66000
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0000
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0001
#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
#define regMMUTCL2_CGTT_CLK_CTRL 0x0002
#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 2
#define regMMMC_SHARED_ACTIVE_FCN_ID 0x0003
#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 2
#define regMMUTCL2_CGTT_BUSY_CTRL 0x0004
#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 2
#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x0005
#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 2
// addressBlock: mmhub_mmutcl2_mmvml2pfdec
// base address: 0x66090
#define regMMVM_L2_CNTL 0x0024
#define regMMVM_L2_CNTL_BASE_IDX 2
#define regMMVM_L2_CNTL2 0x0025
#define regMMVM_L2_CNTL2_BASE_IDX 2
#define regMMVM_L2_CNTL3 0x0026
#define regMMVM_L2_CNTL3_BASE_IDX 2
#define regMMVM_L2_STATUS 0x0027
#define regMMVM_L2_STATUS_BASE_IDX 2
#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0028
#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 2
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0029
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 2
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x002a
#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 2
#define regMMVM_INVALIDATE_CNTL 0x002b
#define regMMVM_INVALIDATE_CNTL_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_CNTL_LO32 0x002c
#define regMMVM_L2_PROTECTION_FAULT_CNTL_LO32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_CNTL_HI32 0x002d
#define regMMVM_L2_PROTECTION_FAULT_CNTL_HI32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x002e
#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x002f
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x0030
#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32 0x0031
#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32 0x0032
#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x0033
#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x0034
#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x0035
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 2
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0036
#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0038
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0039
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x003a
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 2
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x003b
#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 2
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x003c
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 2
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x003d
#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 2
#define regMMVM_L2_CNTL4 0x003e
#define regMMVM_L2_CNTL4_BASE_IDX 2
#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x003fAnnotation
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.